Isolated gate driver, traction inverter, and electric vehicle

ABSTRACT

An isolated gate driver has: a register that stores the adjustment data read from a non-volatile memory; a gate driving circuit that drives the gate of a switching element with a characteristic set based on a value stored in the register; a fault detector that performs fault detection for other than the non-volatile memory; an error detection-correction circuit that performs error detection and error correction on the adjustment data written to the non-volatile memory; a first external terminal for output of the result of fault detection; a second external terminal for output of the result of error detection; and a fault controller that, if a one-bit error is detected in the adjustment data, brings the second external terminal into an error-indicating output state and continues with normal operation of the gate driving circuit and, if a two-or-more-bit error is detected in the adjustment data, forcibly stops the gate driving circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This nonprovisional application is a continuation application ofInternational Patent Application No. PCT/JP2022/002155 filed on Jan. 21,2022, which claims priority Japanese Patent Application No. 2021-042137filed on Mar. 16, 2021, the entire contents of which are herebyincorporated by reference.

TECHNICAL FIELD

The invention disclosed herein relates to isolated gate drivers, andalso relates to traction inverters and electric vehicles that employisolated gate drivers.

BACKGROUND ART

Isolated gate drivers are used in a variety of sets (e.g., tractioninverters for electric vehicles).

One example of known technology related to what is mentioned above isfound in Patent Document 1 identified below.

CITATION LIST Patent Literature

-   Patent Document 1: WO 2011/055611

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating the basic configuration of a signaltransmission device.

FIG. 2 is a diagram illustrating the basic structure of a transformerchip.

FIG. 3 a perspective view of a semiconductor device used as atwo-channel transformer chip.

FIG. 4 is a plan view of the semiconductor device shown in FIG. 3 .

FIG. 5 is a plan view of a layer in the semiconductor device shown inFIG. 3 where low-potential coils are formed.

FIG. 6 is a plan view of a layer in the semiconductor device shown inFIG. 3 where high-potential coils are formed.

FIG. 7 is a cross-sectional view taken along line VIII-VIII shown inFIG. 6 .

FIG. 8 is an enlarged view (showing a separation structure) of regionXIII shown in FIG. 7 .

FIG. 9 is a diagram schematically showing an example of the layout of atransformer chip.

FIG. 10 is a diagram showing the basic configuration of a tractioninverter.

FIG. 11 is a diagram showing a novel embodiment of an isolated gatedriver.

FIG. 12 is a diagram showing a start-up sequence of an isolated gatedriver.

FIG. 13 is a diagram showing a first implementation example of anon-volatile memory.

FIG. 14 is a diagram showing a second implementation example of anon-volatile memory.

FIG. 15 is a diagram showing a third implementation example of anon-volatile memory.

FIG. 16 is a diagram showing a first operation example of fault output.

FIG. 17 is a diagram showing a second operation example of fault output.

FIG. 18 is a diagram showing a third operation example of fault output.

FIG. 19 is a diagram showing a fourth operation example of fault output.

FIG. 20 is a diagram showing a first example of sharing a fault signaloutput terminal.

FIG. 21 is a diagram showing a second example of sharing a fault signaloutput terminal.

FIG. 22 is a diagram showing a third example of sharing a fault signaloutput terminal.

FIG. 23 is a diagram showing the exterior appearance of an electricvehicle.

DESCRIPTION OF EMBODIMENTS

<Signal Transmission Device (Basic Configuration)>

FIG. 1 is a diagram illustrating the basic configuration of a signaltransmission device. The signal transmission device 200 of thisconfiguration example is a semiconductor integrated circuit device (whatis generally called an isolated gate driver IC) that, while isolatingbetween a primary circuit system 200 p (VCC1-GND1 system) and asecondary circuit system 200 s (VCC2-GND2 system), transmits a pulsesignal from the primary circuit system 200 p to the secondary circuitsystem 200 s to drive the gate of a switching device (unillustrated)provided in the secondary circuit system 200 s. The signal transmissiondevice 200 has, for example, a controller chip 210, a driver chip 220,and a transformer chip 230 sealed in a single package.

The controller chip 210 is a semiconductor chip that operates by beingsupplied with a supply voltage VCC1 (e.g., seven volts at the maximumwith respect to GND1). The controller chip 210 has, for example, a pulsetransmission circuit 211 and buffers 212 and 213 integrated in it.

The pulse transmission circuit 211 is a pulse generator that generatestransmission pulse signals S11 and S21 according to an input pulsesignal IN. More specifically, when indicating that the input pulsesignal IN is at high level, the pulse transmission circuit 211pulse-drives (outputs a single or a plurality of pulses in) thetransmission pulse signal S11; when indicating that the input pulsesignal IN is at low level, the pulse transmission circuit 211pulse-drives the transmission pulse signal S21. That is, the pulsetransmission circuit 211 pulse-drives either the transmission pulsesignal S11 or S21 according to the logic level of the input pulse signalIN.

The buffer 212 receives the transmission pulse signal S11 from the pulsetransmission circuit 211, and pulse-drives the transformer chip 230(more specifically, a transformer 231).

The buffer 213 receives the transmission pulse signal S21 from the pulsetransmission circuit 211, and pulse-drives the transformer chip 230(more specifically, a transformer 232).

The driver chip 220 is a semiconductor chip that operates by beingsupplied with a supply voltage VCC2 (e.g., 30 volts at the maximum withrespect to GND2). The driver chip 220 has, for example, buffers 221 and222, a pulse reception circuit 223, and a driver 224 integrated in it.

The buffer 221 performs waveform shaping on a reception pulse signal S12induced in the transformer chip 230 (specifically, the transformer 231),and outputs the result to the pulse reception circuit 223.

The buffer 222 performs waveform shaping on a reception pulse signal S22induced in the transformer chip 230 (specifically, the transformer 232),and outputs the result to the pulse reception circuit 223.

According to the reception pulse signals S12 and S22 fed to it via thebuffers 221 and 222, the pulse reception circuit 223 drivers the driver224 to generate an output pulse signal OUT. More specifically, the pulsereception circuit 223 drives the driver 224 to raise the output pulsesignal OUT to high level in response to the reception pulse signal S12being pulse-driven and to drop the output pulse signal OUT to low levelin response to the reception pulse signal S22 being pulse-driven. Thatis, the pulse reception circuit 223 switches the logic level of theoutput pulse signal OUT according to the logic level of the input pulsesignal IN. As the pulse reception circuit 223, for example, an RSflip-flop can be suitably used.

The driver 224 generates the output pulse signal OUT under the drivingand control of the pulse reception circuit 223.

The transformer chip 230, while isolating between the controller chip210 and the driver chip 220 on a direct-current basis using thetransformers 231 and 232, outputs the transmission pulse signals S11 andS21 fed to the transformer chip 230 from the pulse transmission circuit211 to, as the reception pulse signals S12 and S22, the pulse receptioncircuit 223. In the present description, “isolating on a direct-currentbasis” means leaving two elements to be isolated from each otherunconnected by a conductor.

More specifically, the transformer 231 outputs, according to thetransmission pulse signal S11 fed to the primary coil 231 p, thereception pulse signal S12 from the secondary coil 231 s. Likewise, thetransformer 232 outputs, according to the transmission pulse signal S21fed to the primary coil 232 p, the reception pulse signal S22 from thesecondary coil 232 s.

In this way, owing to the characteristics of spiral coils used inisolated communication, the input pulse signal IN is split into twotransmission pulse signals S11 and S21 (corresponding to a rise signaland a fall signal) to be transmitted via the two transformers 231 and232 from the primary circuit system 200 p to the secondary circuitsystem 200 s.

Note that the signal transmission device 200 of this configurationexample has, separately from the controller chip 210 and the driver chip220, the transformer chip 230 that incorporates the transformers 231 and232 alone, and those three chips are sealed in a single package.

With this configuration, the controller chip 210 and the driver chip 220can each be formed by a common low- to middle-withstand-voltage process(with a withstand voltage of several volts to several tens of volts).This eliminates the need for a dedicated high-withstand-voltage process(with a withstand voltage of several kilovolts), and helps reducemanufacturing costs.

The signal transmission device 200 can be employed suitably, forexample, in a power supply device or motor driving device in avehicle-mounted device incorporated in a vehicle. Such a vehicle can bean engine vehicle or an electric vehicle (an xEV such as a BEV [batteryelectric vehicle], HEV [hybrid electric vehicle], PHEV/PHV [plug-inhybrid electric vehicle/plug-in hybrid vehicle], or FCEV/FCV [fuel cellelectric vehicle/fuel cell vehicle]).

<Transformer Chip (Basic Structure)>

Next, the basic structure of the transformer chip 230 will be described.FIG. 2 is a diagram showing the basic structure of the transformer chip230. In the transformer chip 230 shown there, the transformer 231includes a primary coil 231 p and a secondary coil 231 s that face eachother in the up-down direction; the transformer 232 includes a primarycoil 232 p and a secondary coil 232 s that face each other in theup-down direction.

The primary coils 231 p and 232 p are both formed in a first wiringlayer (lower layer) 230 a in the transformer chip 230. The secondarycoils 231 s and 231 s are both formed in a second wiring layer (theupper layer in the diagram) 230 b in the transformer chip 230. Thesecondary coil 231 s is disposed right above the primary coil 231 p andfaces the primary coil 231 p; the secondary coil 232 s is disposed rightabove the primary coil 232 p and faces the primary coil 232 p.

The primary coil 231 p is laid in a spiral shape so as to encircle aninternal terminal X21 clockwise, starting at the first terminal of theprimary coil 231 p, which is connected to the internal terminal X21. Thesecond terminal of the primary coil 231 p, which corresponds to its endpoint, is connected to an internal terminal X22 Likewise, the primarycoil 232 p is laid in a spiral shape so as to encircle an internalterminal X23 anticlockwise, starting at the first terminal of theprimary coil 232 p, which is connected to the internal terminal X23. Thesecond terminal of the primary coil 232 p, which corresponds to its endpoint, is connected to the internal terminal X22. The internal terminalsX21, X22, and X23 are arrayed on a straight line in the illustratedorder.

The internal terminal X21 is connected, via a wiring Y21 and a via Z21both conductive, to an external terminal T21 in the second layer 230 b.The internal terminal X22 is connected, via a wiring Y22 and a via Z22both conductive, to an external terminal T22 in the second layer 230 b.The internal terminal X23 is connected, via a wiring Y23 and a via Z23both conductive, to an external terminal T23 in the second layer 230 b.The external terminals T21 to T23 are disposed in a straight row and areused for wire-bonding with the controller chip 210.

The secondary coil 231 s is laid in a spiral shape so as to encircle anexternal terminal T24 anticlockwise, starting at the first terminal ofthe secondary coil 231 s, which is connected to the external terminalT24. The second terminal of the secondary coil 231 s, which correspondsto its end point, is connected to an external terminal T25. Likewise,the secondary coil 232 s is laid in a spiral shape so as to encircle anexternal terminal T26 clockwise, starting at the first terminal of thesecondary coil 232 s, which is connected to the external terminal T26.The second terminal of the secondary coil 232 s, which corresponds toits end point, is connected to the external terminal T25. The externalterminals T24, T25, and T26 are disposed in a straight row in theillustrated order and are used for wire-bonding with the driver chip220.

The secondary coils 231 s and 232 s are AC-connected to the primarycoils 231 p and 232 p, respectively, by magnetic coupling, and areDC-isolated from the primary coils 231 p and 232 p. That is, the driverchip 220 is AC-connected to the controller chip 210 via the transformerchip 230, and is DC-isolated from the controller chip 210 by thetransformer chip 230.

<Transformer Chip (Two-Channel Type)>

FIG. 3 is a perspective view of a semiconductor device 5 used as atwo-channel transformer chip. FIG. 4 is a plan view of the semiconductordevice 5 shown in FIG. 3 . FIG. 5 is a plan view showing a layer in thesemiconductor device 5 shown in FIG. 3 where low-potential coils 22(corresponding to the primary coils of transformers) are formed. FIG. 6is a plan view showing a layer in the semiconductor device 5 shown inFIG. 3 where high-potential coils 23 (corresponding to the secondarycoils of transformers) are formed. FIG. 7 is a sectional view along lineVIII-VIII shown in FIG. 6 . FIG. 8 is an enlarged view of region XIIIshown in FIG. 7 , showing a separation structure 130.

Referring to FIGS. 3 to 7 , the semiconductor device 5 includes asemiconductor chip 41 in the shape of a rectangular parallelepiped. Thesemiconductor chip 41 contains at least one of silicon, a wide band gapsemiconductor, and a compound semiconductor.

The wide band gap semiconductor is a semiconductor with a band gaplarger than that of silicon (about 1.12 eV). Preferably, the wide bandgap semiconductor has a band gap of 2.0 eV or more. The wide band gapsemiconductor can be SiC (silicon carbide). The compound semiconductorcan be a III-V group compound semiconductor. The compound semiconductorcan contain at least one of aluminum nitride (AlN), indium nitride(InN), gallium nitride (GaN), and gallium arsenide (GaAs).

In the embodiment, the semiconductor chip 41 includes a semiconductorsubstrate made of silicon. The semiconductor chip 41 can be an epitaxialsubstrate that has a stacked structure composed of a semiconductorsubstrate made of silicon and an epitaxial layer made of silicon. Thesemiconductor substrate can be of an n-type or p-type conductivity. Theepitaxial layer can be of an n-type or p-type.

The semiconductor chip 41 has a first principal surface 42 at one side,a second principal surface 43 at the other side, and chip side walls 44Ato 44D that connect the first and second principal surfaces 42 and 43together. As seen in a plan view from the normal direction Z to them(hereinafter simply expressed as “as seen in a plan view”), the firstand second principal surfaces 42 and 43 are each formed in aquadrangular shape (in the embodiment, in a rectangular shape).

The chip side walls 44A to 44D includes a first chip side wall 44A, asecond chip side wall 44B, a third chip side wall 44C, and a fourth chipside wall 44D. The first and second chip side walls 44A and 44Bconstitute the longer sides of the semiconductor chip 41. The first andsecond chip side walls 44A and 44B extend along a first direction X andface away from each other in a second direction Y. The third and fourthchip side walls 44C and 44D constitute the shorter sides of thesemiconductor chip 41. The third and fourth chip side walls 44C and 44Dextend in the second direction Y and face away from each other in thefirst direction X. The chip side walls 44A to 44D have polishedsurfaces.

The semiconductor device 5 further includes an insulation layer 51formed on the first principal surface 42 of the semiconductor chip 41.The insulation layer 51 has an insulation principal surface 52 andinsulation side walls 53A to 53D. The insulation principal surface 52 isformed in a quadrangular shape (in the embodiment, a rectangular shape)that fits the first principal surface 42 as seen in a plan view. Theinsulation principal surface 52 extends parallel to the first principalsurface 42.

The insulation side walls 53A to 53D include a first insulation sidewall 53A, a second insulation side wall 53B, a third insulation sidewall 53C, and a fourth insulation side wall 53D. The insulation sidewalls 53A to 53D extend from the circumferential edge of the insulationprincipal surface 52 toward the semiconductor chip 41, and arecontinuous with the chip side walls 44A to 44D. Specifically, theinsulation side walls 53A to 53D are formed to be flush with the chipside walls 44A to 44D. The insulation side walls 53A to 53D constitutepolished surfaces that are flush with the chip side walls 44A to 44D.

The insulation layer 51 has a stacked structure of multilayer insulationlayers that include a bottom insulation layer 55, a top insulation layer56, and a plurality of (in the embodiment, eleven) interlayer insulationlayers 57. The bottom insulation layer 55 is an insulation layer thatdirectly covers the first principal surface 42. The top insulation layer56 is an insulation layer that constitutes the insulation principalsurface 52. The plurality of interlayer insulation layers 57 areinsulation layers that are interposed between the bottom and topinsulation layers 55 and 56. In the embodiment, the bottom insulationlayer 55 has a single-layer structure that contains silicon oxide. Inthe embodiment, the top insulation layer 56 has a single-layer structurethat contains silicon oxide. The bottom and top insulation layers 55 and56 can each have a thickness of 1 μm or more but 3 μm or less (e.g.,about 2 μm).

The plurality of interlayer insulation layers 57 each have a stackedstructure that includes a first insulation layer 58 at the bottominsulation layer 55 side and a second insulation layer 59 at the topinsulation layer 56 side. The first insulation layer 58 can containsilicon nitride. The first insulation layer 58 is formed as an etchingstopper layer for the second insulation layer 59. The first insulationlayer 58 can have a thickness of 0.1 μm or more but 1 μm or less (e.g.,about 0.3 μm).

The second insulation layer 59 is formed on top of the first insulationlayer 58, and contains an insulating material different from that of thefirst insulation layer 58. The second insulation layer 59 can containsilicon oxide. The second insulation layer 59 can have a thickness of 1μm or more but 3 μm or less (e.g., about 2 μm). Preferably, the secondinsulation layer 59 is given a thickness larger than that of the firstinsulation layer 58.

The insulation layer 51 can have a total thickness DT of 5 μm or morebut 50 μm or less. The insulation layer 51 can have any total thicknessDT and any number of interlayer insulation layers 57 stacked together,which are adjusted according to the desired dielectric strength voltage(dielectric breakdown withstand voltage). The bottom insulation layer55, the top insulation layer 56, and the interlayer insulation layers 57can employ any insulating material, which is thus not limited to anyparticular insulating material.

The semiconductor device 5 includes a first functional device 45 formedin the insulation layer 51. The first functional device 45 includes oneor a plurality of (in the embodiment, a plurality of) transformers 21(corresponding the transformers mentioned previously). That is, thesemiconductor device 5 is a multichannel device that includes aplurality of transformers 21. The plurality of transformers 21 areformed in an inner part of the insulation layer 51, at intervals fromthe insulation side walls 53A to 53D. The plurality of transformers 21are formed at intervals from each other in the first direction X.

Specifically, the plurality of transformers 21 include a firsttransformer 21A, a second transformer 21B, a third transformer 21C, anda fourth transformer 21D that are formed in this order from theinsulation side wall 53C side to the insulation side wall 53D side asseen in a plan view. The plurality of transformers 21A to 21D havesimilar structures. In the following description, the structure of thefirst transformer 21A will be described as an example. No separatedescription will be given of the structures of the second, third, andfourth transformers 21B, 21C, and 21D, to which the description of thestructure of the first transformer 21A is to be taken to apply.

Referring to FIGS. 5 to 7 , the first transformer 21A includes alow-potential coil 22 and a high-potential coil 23. The low-potentialcoil 22 is formed in the insulation layer 51. The high-potential coil 23is formed in the insulation layer 51 so as to face the low-potentialcoil 22 in the normal direction Z. In the embodiment, the low- andhigh-potential coils 22 and 23 are formed in a region between the bottomand top insulation layers 55 and 56 (i.e., in the plurality ofinterlayer insulation layer 57).

The low-potential coil 22 is formed in the insulation layer 51, at thebottom insulation layer 55 (semiconductor chip 41) side, and thehigh-potential coil 23 is formed in the insulation layer 51, at the topinsulation layer 56 (insulation principal surface 52) side with respectto the low-potential coil 22. That is, the high-potential coil 23 facesthe semiconductor chip 41 across the low-potential coil 22. The low- andhigh-potential coils 22 and 23 can be disposed at any places. Thehigh-potential coil 23 can face the low-potential coil 22 across one ormore interlayer insulation layers 57.

The distance between the low- and high-potential coils 22 and 23 (i.e.,the number of interlayer insulation layers 57 stacked together) isadjusted appropriately according to the dielectric strength voltage andelectric field strength between the low- and high-potential coils 22 and23. In the embodiment, the low-potential coil 22 is formed in the thirdinterlayer insulation layer 57 as counted from the bottom insulationlayer 55 side. In the embodiment, the high-potential coil 23 is formedin the first interlayer insulation layer 57 as counted from the topinsulation layer 56 side.

The low-potential coil 22 is embedded in the interlayer insulation layer57 so as to penetrate the first and second insulation layers 58 and 59.The low-potential coil 22 includes a first inner end 24, a first outerend 25, and a first spiral portion 26 that is patterned in a spiralshape between the first inner and outer ends 24 and 25. The first spiralportion 26 is patterned in a spiral shape that extends in an elliptical(oval) shape as seen in a plan view. The part of the first spiralportion 26 that forms its inner circumferential edge defines a firstinner region 66 that is in an elliptical shape as seen in a plan view.

The first spiral portion 26 can have a number of turns of 5 or more but30 or less. The first spiral portion 26 can have a width of 0.1 μm ormore but 5 μm or less. Preferably, the first spiral portion 26 has awidth of 1 μm or more but 3 μm or less. The width of the first spiralportion 26 is defined by its width in the direction orthogonal to thespiraling direction. The first spiral portion 26 has a first windingpitch of 0.1 μm or more but 5 μm or less. Preferably, the first windingpitch is 1 μm or more but 3 μm or less. The first winding pitch isdefined by the distance between two parts of the first spiral portion 26that are adjacent to each other in the direction orthogonal to thespiraling direction.

The first spiral portion 26 can have any winding shape and the firstinner region 66 can have any planar shape, which are thus not limited tothose shown in FIG. 5 etc. The first spiral portion 26 can be wound in apolygonal shape, such as a triangular or quadrangular shape, or in acircular shape as seen in a plan view. The first inner region 66 can bedefined, so as to fit the winding shape of the first spiral portion 26,in a polygonal shape, such as a triangular or quadrangular shape, or ina circular shape as seen in a plan view.

The low-potential coil 22 can contain at least one of titanium, titaniumnitride, copper, aluminum, and tungsten. The low-potential coil 22 canhave a stacked structure composed of a barrier layer and a body layer.The barrier layer defines a recessed space in the interlayer insulationlayer 57. The barrier layer can contain at least one of titanium andtitanium nitride. The body layer can contain at least one of copper,aluminum, and tungsten.

The high-potential coil 23 is embedded in the interlayer insulationlayer 57 so as to penetrate the first and second insulation layers 58and 59. The high-potential coil 23 includes a second inner end 27, asecond outer end 28, and a second spiral portion 29 that is patterned ina spiral shape between the second inner and outer ends 27 and 28. Thesecond spiral portion 29 is patterned in a spiral shape that extends inan elliptical (oval) shape as seen in a plan view. The part of thesecond spiral portion 29 that forms its inner circumferential edgedefines a second inner region 67 that is in an elliptical shape as seenin a plan view in the embodiment. The second inner region 67 in thesecond spiral portion 29 faces the first inner region 66 in the firstspiral portion 26 in the normal direction Z.

The second spiral portion 29 can have a number of turns of 5 or more but30 or less. The number of turns of the second spiral portion 29 relativeto that of the first spiral portion 26 is adjusted according to thetarget value of voltage boosting. Preferably, the number of turns of thesecond spiral portion 29 is larger than that of the first spiral portion26. Needless to say, the number of turns of the second spiral portion 29can be smaller than or equal to that of the first spiral portion 26.

The second spiral portion 29 can have a width of 0.1 μm or more but 5 μmor less. Preferably, the second spiral portion 29 has a width of 1 μm ormore but 3 μm or less. The width of the second spiral portion 29 isdefined by its width in the direction orthogonal to the spiralingdirection. Preferably, the width of the second spiral portion 29 isequal to the width of the first spiral portion 26.

The second spiral portion 29 can have a second winding pitch of 0.1 μmor more but 5 μm or less. Preferably, the second winding pitch is 1 μmor more but 3 μm or less. The second winding pitch is defined by thedistance between two parts of the second spiral portion 29 that areadjacent to each other in the direction orthogonal to the spiralingdirection. Preferably, the second winding pitch is equal to the firstwinding pitch of the first spiral portion 26.

The second spiral portion 29 can have any winding shape and the secondinner region 67 can have any planar shape, which are thus not limited tothose shown in FIG. 6 etc. The second spiral portion 29 can be wound ina polygonal shape, such as a triangular or quadrangular shape, or in acircular shape as seen in a plan view. The second inner region 67 can bedefined, so as to fit the winding shape of the second spiral portion 29,in a polygonal shape, such as a triangular or quadrangular shape, or ina circular shape as seen in a plan view.

Preferably, the high-potential coil 23 is formed of the same conductivematerial as the low-potential coil 22. That is, preferably, like thelow-potential coil 22, the high-potential coil 23 includes a barrierlayer and a body layer.

Referring to FIG. 4 , the semiconductor device 5 includes a plurality of(in the diagram, twelve) low-potential terminals 11 and a plurality of(in the diagram, twelve) high-potential terminals 12. The plurality oflow-potential terminals 11 are electrically connected to thelow-potential coils 22 of the corresponding transformers 21A to 21Drespectively. The plurality of high-potential terminals 12 areelectrically connected to the high-potential coils 23 of thecorresponding transformers 21A to 21D respectively.

The plurality of low-potential terminals 11 are formed on the insulationprincipal surface 52 of the insulation layer 51. Specifically, theplurality of low-potential terminals 11 are formed in a secondinsulation side wall 53B side region, at an interval from the pluralityof transformers 21A to 21D in the second direction Y, and are arrayed atintervals from each other in the first direction X.

The plurality of low-potential terminals 11 include a firstlow-potential terminal 11A, a second low-potential terminal 11B, a thirdlow-potential terminal 11C, a fourth low-potential terminal 11D, a fifthlow-potential terminal 11E, and a sixth low-potential terminal 11F.Actually, in the embodiment, two each of the plurality of low-potentialterminals 11A to 11F are formed. The plurality of low-potentialterminals 11A to 11F may each include any number of terminals.

The first low-potential terminal 11A faces the first transformer 21A inthe second direction Y as seen in a plan view. The second low-potentialterminal 11B faces the second transformer 21B in the second direction Yas seen in a plan view. The third low-potential terminal 11C faces thethird transformer 21C in the second direction Y as seen in a plan view.The fourth low-potential terminal 11D faces the fourth transformer 21Din the second direction Y as seen in a plan view. The fifthlow-potential terminal 11E is formed in a region between the first andsecond low-potential terminals 11A and 11B as seen in a plan view. Thesixth low-potential terminal 11F is formed in a region between the thirdand fourth low-potential terminals 11C and 11D as seen in a plan view.

The first low-potential terminal 11A is electrically connected to thefirst inner end 24 of the first transformer 21A (low-potential coil 22).The second low-potential terminal 11B is electrically connected to thefirst inner end 24 of the second transformer 21B (low-potential coil22). The third low-potential terminal 11C is electrically connected tothe first inner end 24 of the third transformer 21C (low-potential coil22). The fourth low-potential terminal 11D is electrically connected tothe first inner end 24 of the fourth transformer 21D (low-potential coil22).

The fifth low-potential terminal 11E is electrically connected to thefirst outer end 25 of the first transformer 21A (low-potential coil 22)and to the first outer end 25 of the second transformer 21B(low-potential coil 22). The sixth low-potential terminal 11F iselectrically connected to the first outer end 25 of the thirdtransformer 21C (low-potential coil 22) and to the first outer end 25 ofthe fourth transformer 21D (low-potential coil 22).

The plurality of high-potential terminals 12 are formed on theinsulation principal surface 52 of the insulation layer 51, at aninterval from the plurality of low-potential terminals 11. Specifically,the plurality of high-potential terminals 12 are formed in a firstinsulation side wall 53A side region, at an interval from the pluralityof low-potential terminals 11 in the second direction Y, and are arrayedat intervals from each other in the first direction X.

The plurality of high-potential terminals 12 are formed in regions closeto the corresponding transformers 21A to 21D, respectively, as seen in aplan view. The high-potential terminals 12 being close to thetransformers 21A to 21D means that, as seen in a plan view, the distancebetween the high-potential terminals 12 and the transformers 21 issmaller than the distance between the low-potential terminals 11 and thehigh-potential terminals 12.

Specifically, as seen in a plan view, the plurality of high-potentialterminals 12 are formed at intervals from each other along the firstdirection X so as to face the plurality of transformers 21A to 21D alongthe first direction X. More specifically, as seen in a plan view, theplurality of high-potential terminals 12 are formed at intervals fromeach other along the first direction X so as to be located in the secondinner regions 67 in the high-potential coils 23 and in regions betweenadjacent high-potential coils 23. As a result, as seen in a plan view,the plurality of high-potential terminals 12 are, along with thetransformers 21A to 21D, arrayed in one row along the first direction X.

The plurality of high-potential terminals 12 include a firsthigh-potential terminal 12A, a second high-potential terminal 12B, athird high-potential terminal 12C, a fourth high-potential terminal 12D,a fifth high-potential terminal 12E, and a sixth high-potential terminal12F. Actually, in the embodiment, two each of the plurality ofhigh-potential terminals 12A to 12F are formed. The plurality ofhigh-potential terminals 12A to 12F may each include any number ofterminals.

The first high-potential terminal 12A is formed in the second innerregion 67 in the first transformer 21A (high-potential coil 23) as seenin a plan view. The second high-potential terminal 12B is formed in thesecond inner region 67 in the second transformer 21B (high-potentialcoil 23) as seen in a plan view. The third high-potential terminal 12Cis formed in the second inner region 67 in the third transformer 21C(high-potential coil 23) as seen in a plan view. The fourthhigh-potential terminal 12D is formed in the second inner region 67 inthe fourth transformer 21D (high-potential coil 23) as seen in a planview. The fifth high-potential terminal 12E is formed in a regionbetween the first and second transformers 21A and 21B as seen in a planview. The sixth high-potential terminal 12F is formed in a regionbetween the third and fourth transformers 21C and 21D as seen in a planview.

The first high-potential terminal 12A is electrically connected to thesecond inner end 27 of the first transformer 21A (high-potential coil23). The second high-potential terminal 12B is electrically connected tothe second inner end 27 of the second transformer 21B (high-potentialcoil 23). The third high-potential terminal 12C is electricallyconnected to the second inner end 27 of the third transformer 21C(high-potential coil 23). The fourth high-potential terminal 12D iselectrically connected to the second inner end 27 of the fourthtransformer 21D (high-potential coil 23).

The fifth high-potential terminal 12E is electrically connected to thesecond outer end 28 of the first transformer 21A (high-potential coil23) and to the second outer end 28 of the second transformer 21B(high-potential coil 23). The sixth high-potential terminal 12F iselectrically connected to the second outer end 28 of the thirdtransformer 21C (high-potential coil 23) and to the second outer end 28of the fourth transformer 21D (high-potential coil 23).

Referring to FIGS. 5 and 7 , the semiconductor device 5 includes a firstlow-potential wiring 31, a second low-potential wiring 32, a firsthigh-potential wiring 33, and a second high-potential wiring 34, allformed in the insulation layer 51. Actually, in the embodiment, aplurality of first low-potential wirings 31, a plurality of secondlow-potential wirings 32, a plurality of first high-potential wirings33, and a plurality of second high-potential wirings 34 are formed.

The first and second low-potential wirings 31 and 32 hold thelow-potential coils 22 of the first and second transformers 21A and 21Bat equal potentials. The first and second low-potential wirings 31 and32 also hold the low-potential coils 22 of the third and fourthtransformers 21C and 21D at equal potentials. In the embodiment, thefirst and second low-potential wirings 31 and 32 hold the low-potentialcoils 22 of all the transformers 21A to 21D at equal potentials.

The first and second high-potential wirings 33 and 34 hold thehigh-potential coils 23 of the first and second transformers 21A and 21Bat equal potentials. The first and second high-potential wirings 33 and34 also hold the high-potential coils 23 of the third and fourthtransformers 21C and 21D at equal potentials. In the embodiment, thefirst and second high-potential wirings 33 and 34 hold thehigh-potential coils 23 of all the transformers 21A to 21D at equalpotentials.

The plurality of first low-potential wirings 31 are electricallyconnected respectively to the corresponding low-potential terminals 11Ato 11D and to the first inner ends 24 of the corresponding transformers21A to 21D (low-potential coils 22). The plurality of firstlow-potential wirings 31 have similar structures. In the followingdescription, the structure of the first low-potential wiring 31connected to the first low-potential terminal 11A and to the firsttransformer 21A will be described as an example. No separate descriptionwill be given of the structures of the other first low-potential wirings31, to which the description of the structure of the first low-potentialwiring 31 connected to the first transformer 21A is to be taken toapply.

The first low-potential wiring 31 includes a through wiring 71, alow-potential connection wiring 72, a lead wiring 73, a first connectionplug electrode 74, a second connection plug electrode 75, one or aplurality of (in this embodiment, a plurality of) pad plug electrodes76, and one or a plurality of (in this embodiment, a plurality of)substrate plug electrodes 77.

Preferably, the through wiring 71, the low-potential connection wiring72, the lead wiring 73, the first connection plug electrode 74, thesecond connection plug electrode the pad plug electrodes 76, and thesubstrate plug electrodes 77 are formed of the same conductive materialas the low-potential coil 22 and the like. That is, preferably, like thelow-potential coil 22 and the like, the through wiring 71, thelow-potential connection wiring 72, the lead wiring 73, the firstconnection plug electrode 74, the second connection plug electrode 75,the pad plug electrodes 76, and the substrate plug electrodes 77 eachinclude a barrier layer and a body layer.

The through wiring 71 penetrates a plurality of interlayer insulationlayers 57 in the insulation layer 51 and extends in a columnar shapealong the normal direction Z. In the embodiment, the through wiring 71is formed in a region between the bottom and top insulation layers 55and 56 in the insulation layer 51. The through wiring 71 has a top endpart at the top insulation layer 56 side and a bottom end part at thebottom insulation layer 55 side. The top end part of the through wiring71 is formed in the same interlayer insulation layer 57 as thehigh-potential coil 23, and is covered by the top insulation layer 56.The bottom end part of the through wiring 71 is formed in the sameinterlayer insulation layer 57 as the low-potential coil 22.

In the embodiment, the through wiring 71 includes a first electrodelayer 78, a second electrode layer 79, and a plurality of wiring plugelectrodes 80. In the through wiring 71, the first and second electrodelayers 78 and 79 and the wiring plug electrodes are formed of the sameconductive material as the low-potential coil 22 and the like. That is,like the low-potential coil 22 and the like, the first and secondelectrode layers 78 and 79 and the wiring plug electrodes 80 eachinclude a barrier layer and a body layer.

The first electrode layer 78 constitutes the top end part of the throughwiring 71. The second electrode layer 79 constitutes the bottom end partof the through wiring 71. The first electrode layer 78 is formed as anisland, and faces the low-potential terminal 11 (first low-potentialterminal 11A) in the normal direction Z. The second electrode layer 79is formed as an island, and faces the first electrode layer 78 in thenormal direction Z.

The plurality of wiring plug electrodes 80 are embedded respectively inthe plurality of interlayer insulation layers 57 located in a regionbetween the first and second electrode layers 78 and 79. The pluralityof wiring plug electrodes 80 are stacked together from the bottominsulation layer 55 to the top insulation layer 56 so as to beelectrically connected together, and electrically connect together thefirst and second electrode layers 78 and 79. The plurality of wiringplug electrodes 80 each have a plane area smaller than the plane area ofeither of the first and second electrode layers 78 and 79.

The number of layers stacked in the plurality of wiring plug electrodes80 is equal to the number of layers stacked in the plurality ofinterlayer insulation layer 57. In the embodiment, six wiring plugelectrodes 80 are embedded in interlayer insulation layers 57respectively, and any number of wiring plug electrodes 80 can beembedded in interlayer insulation layers 57 respectively. Needless tosay, one or a plurality of wiring plug electrodes 80 can be formed thatpenetrates a plurality of interlayer insulation layers 57.

The low-potential connection wiring 72 is formed in the same interlayerinsulation layer 57 as the low-potential coil 22, in the first innerregion 66 in the first transformer 21A (low-potential coil 22). Thelow-potential connection wiring 72 is formed as an island, and faces thehigh-potential terminal 12 (first high-potential terminal 12A) in thenormal direction Z. Preferably, the low-potential connection wiring 72has a plane area larger than the plane area of the wiring plug electrode80. The low-potential connection wiring 72 is electrically connected tothe first inner end 24 of the low-potential coil 22.

The lead wiring 73 is formed in the interlayer insulation layer 57, in aregion between the semiconductor chip 41 and the through wiring 71. Inthe embodiment, the lead wiring 73 is formed in the first interlayerinsulation layer 57 as counted from the bottom insulation layer 55. Thelead wiring 73 has a first end part at one side, a second end part atthe other side, and a wiring part that connects together the first andsecond end parts. The first end part of the lead wiring 73 is located ina region between the semiconductor chip 41 and the bottom end part ofthe through wiring 71. The second end part of the lead wiring 73 islocated in a region between the semiconductor chip 41 and thelow-potential connection wiring 72. The wiring part extends along thefirst principal surface 42 of the semiconductor chip 41, and extends inthe shape of a stripe in a region between the first and second endparts.

The first connection plug electrode 74 is formed in the interlayerinsulation layer 57, in a region between the through wiring 71 and thelead wiring 73, and is electrically connected to the through wiring 71and to the first end part of the lead wiring 73. The second connectionplug electrode 75 is formed in the interlayer insulation layer 57, in aregion between the low-potential connection wiring 72 and the leadwiring 73, and is electrically connected to the low-potential connectionwiring 72 and to the second end part of the lead wiring 73.

The plurality of pad plug electrodes 76 are formed in the top insulationlayer 56, in a region between the low-potential terminal 11 (firstlow-potential terminal 11A) and the through wiring 71, and areelectrically connected to the low-potential terminal 11 and to the topend part of the through wiring 71. The plurality of substrate plugelectrodes 77 are formed in the bottom insulation layer 55, in a regionbetween the semiconductor chip 41 and the lead wiring 73. In theembodiment, the substrate plug electrodes 77 are formed in a regionbetween the semiconductor chip 41 and the first end part of the leadwiring 73, and are electrically connected to the semiconductor chip 41and to the first end part of the lead wiring 73.

Referring to FIGS. 6 and 7 , the plurality of first high-potentialwirings 33 are connected respectively to the correspondinghigh-potential terminals 12A to 12D and to the second inner ends 27 ofthe corresponding transformers 21A to 21D (high-potential coils 23). Theplurality of first high-potential wirings 33 have similar structures. Inthe following description, the structure of the first high-potentialwiring 33 connected to the first high-potential terminal 12A and to thefirst transformer 21A will be described as an example. No descriptionwill be given of the structures of the other first high-potentialwirings 33, to which the description of the structure of the firsthigh-potential wiring 33 connected to the first transformer 21A is to betaken to apply.

The first high-potential wiring 33 includes a high-potential connectionwiring 81 and one or a plurality of (in this embodiment, a plurality of)pad plug electrodes 82. Preferably, the high-potential connection wiring81 and the pad plug electrodes 82 are formed of the same conductivematerial as the low-potential coil 22 and the like. That is, preferably,like the low-potential coil 22 and the like, the high-potentialconnection wiring 81 and the pad plug electrodes 82 each include abarrier layer and a body layer.

The high-potential connection wiring 81 is formed in the same interlayerinsulation layer 57 as the high-potential coil 23, in the second innerregion 67 in the high-potential coil 23. The high-potential connectionwiring 81 is formed as an island, and faces the high-potential terminal12 (first high-potential terminal 12A) in the normal direction Z. Thehigh-potential connection wiring 81 is electrically connected to thesecond inner end 27 of the high-potential coil 23. The high-potentialconnection wiring 81 is formed at an interval from the low-potentialconnection wiring 72 as seen in a plan view, and does not face thelow-potential connection wiring 72 in the normal direction Z. Thisresults in an increased insulation distance between the low- andhigh-potential connection wirings 72 and 81 and hence an increaseddielectric strength voltage in the insulation layer 51.

The plurality of pad plug electrodes 82 are formed in the top insulationlayer 56, in a region between the high-potential terminal 12 (firsthigh-potential terminal 12A) and the high-potential connection wiring81, and are electrically connected to the high-potential terminal 12 andto the high-potential connection wiring 81. The plurality of pad plugelectrodes 82 each have a plane area smaller than the plane area of thehigh-potential connection wiring 81 as seen in a plan view.

Referring to FIG. 7 , preferably, the distance D1 between the low- andhigh-potential terminals 11 and 12 is larger than the distance D2between the low- and high-potential coils 22 and 23 (D2<D1). Preferably,the distance D1 is larger than the total thickness DT of the pluralityof interlayer insulation layers 57 (DT<D1). The ratio D2/D1 of thedistance D2 to the distance D1 can be 0.01 or more but 0.1 or less.Preferably, the distance D1 is 100 μm or more but 500 μm or less. Thedistance D2 can be 1 μm or more but 50 μm or less. Preferably, thedistance D2 is 5 μm or more but 25 μm or less. The distances D1 and D2can have any values, which are adjusted appropriately according to thedesired dielectric strength voltage.

Referring to FIGS. 6 and 7 , the semiconductor device 5 has a dummypattern 85 that is embedded in the insulation layer 51 so as to belocated around the transformers 21A to 21D as seen in a plan view.

The dummy pattern 85 is formed in a pattern different (discontinuous)from that of either of the high- and low-potential coils 23 and 22, andis independent of the transformers 21A to 21D. That is, the dummypattern 85 does not function as part of the transformers 21A to 21D. Thedummy pattern 85 is formed as a shield conductor layer that shieldselectric fields between the low- and high-potential coils 22 and 23 inthe transformers 21A to 21D to suppress electric field concentration onthe high-potential coil 23. In the embodiment, the dummy pattern 85 ispatterned at a line density per unit area that is equal to the linedensity of the high-potential coil 23. The line density of the dummypattern 85 being equal to the line density of the high-potential coil 23means that the line density of the dummy pattern 85 falls within therange of ±20% of the line density of the high-potential coil 23.

The dummy pattern 85 can be formed at any depth in the insulation layer51, which is adjusted according to the electric field strength to beattenuated. Preferably, the dummy pattern 85 is formed in a regioncloser to the high-potential coil 23 than to the low-potential coil 22with respect to the normal direction Z. The dummy pattern 85 beingcloser to the high-potential coil 23 with respect to the normaldirection Z means that, with respect to the normal direction Z, thedistance between the dummy pattern 85 and the high-potential coil 23 issmaller than the distance between the dummy pattern 85 and thelow-potential coil 22.

In that way, electric field concentration on the high-potential coil 23can be suppressed properly. The smaller the distance between the dummypattern 85 and the high-potential coil 23 with respect to the normaldirection Z, the more effectively electric field concentration on thehigh-potential coil 23 can be suppressed. Preferably, the dummy pattern85 is formed in the same interlayer insulation layer 57 as thehigh-potential coil 23. In that way, electric field concentration on thehigh-potential coil 23 can be suppressed more properly. The dummypattern 85 includes a plurality of dummy patterns that are in varyingelectrical states. The dummy pattern 85 can include a high-potentialdummy pattern.

The high-potential dummy pattern 86 can be formed at any depth in theinsulation layer 51, which is adjusted according to the electric fieldstrength to be attenuated. Preferably, the high-potential dummy pattern86 is formed in a region closer to the high-potential coil 23 than tothe low-potential coil 22 with respect to the normal direction Z. Thehigh-potential dummy pattern 86 being closer to the high-potential coil23 with respect to the normal direction Z means that, with respect tothe normal direction Z, the distance between the high-potential dummypattern 86 and the high-potential coil 23 is smaller than the distancebetween the high-potential dummy pattern 86 and the low-potential coil22.

The dummy pattern 85 includes a floating dummy pattern that is formed inan electrically floating state in the insulation layer 51 so as to belocated around the transformers 21A to 21D.

In the embodiment, the floating dummy pattern is patterned in denselines so as to partly cover and partly expose a region around thehigh-potential coil 23 as seen in a plan view. The floating dummypattern can be formed so as to have ends or no ends.

The floating dummy pattern can be formed at any depth in the insulationlayer 51, which is adjusted according to the electric field strength tobe attenuated.

Any number of floating lines can be provided, which is adjustedaccording to the electric field strength to be attenuated. The floatingdummy pattern can include a plurality of floating lines.

Referring to FIG. 7 , the semiconductor device 5 includes a secondfunctional device 60 that is formed in the first principal surface 42 ofthe semiconductor chip 41 in a device region 62. The second functionaldevice 60 is formed using a superficial part of the first principalsurface 42 and/or a region on the first principal surface 42 of thesemiconductor chip 41, and is covered by the insulation layer 51 (bottominsulation layer 55). In FIG. 7 , the second functional device 60 isshown in a simplified form by broken lines indicated in a superficialpart of the first principal surface 42.

The second functional device 60 is electrically connected to alow-potential terminal 11 via a low-potential wiring, and iselectrically connected to a high-potential terminal 12 via ahigh-potential wiring. Except that the low-potential wiring is patternedin the insulation layer 51 so as to be connected to the secondfunctional device 60, it has a similar structure to the firstlow-potential wiring 31 (second low-potential wiring 32). Except thatthe high-potential wiring is patterned in the insulation layer 51 so asto be connected to the second functional device 60, it has a similarstructure to the first high-potential wiring 33 (second high-potentialwiring 34). No description will be given of the low- and high-potentialwirings associated with the second functional device 60.

The second functional device 60 can include at least one of a passivedevice, a semiconductor rectification device, and a semiconductorswitching device. The second functional device 60 can include a circuitnetwork comprising a selective combination of any two or more of apassive device, a semiconductor rectification device, and asemiconductor switching device. The circuit network can constitute partor the whole of an integrated circuit.

The passive device can include a semiconductor passive device. Thepassive device can include one or both of a resistor and a capacitor.The semiconductor rectification device can include at least one of apn-junction diode, a PIN diode, a Zener diode, a Schottky barrier diode,and a fast-recovery diode. The semiconductor switching device caninclude at least one of a BJT (bipolar junction transistor), a MISFET(metal-insulator-semiconductor field-effect transistor), an IGBT(insulated-gate bipolar junction transistor), and a JFET (junctionfield-effect transistor).

Referring to FIGS. 5 to 7 , the semiconductor device 5 further includesa sealing conductor 61 embedded in the insulation layer 51. The sealingconductor 61 is embedded in the form of walls in the insulation layer51, at intervals from the insulation side walls 53A to 53D as seen in aplan view, and partitions the insulation layer 51 into the device region62 and an outer region 63. The sealing conductor 61 prevents moistureentry and crack development from the outer region 63 to the deviceregion 62.

The device region 62 is a region that includes the first functionaldevice 45 (plurality of transformers 21), the second functional device60, the plurality of low-potential terminals 11, the plurality ofhigh-potential terminals 12, the first low-potential wirings 31, thesecond low-potential wirings 32, the first high-potential wirings 33,the second high-potential wirings 34, and the dummy pattern 85. Theouter region 63 is a region outside the device region 62.

The sealing conductor 61 is electrically isolated from the device region62. Specifically, the sealing conductor 61 is electrically isolated fromthe first functional device 45 (plurality of transformers 21), thesecond functional device 60, the plurality of low-potential terminals11, the plurality of high-potential terminals 12, the firstlow-potential wirings 31, the second low-potential wirings 32, the firsthigh-potential wirings 33, the second high-potential wirings 34, and thedummy pattern 85. More specifically, the sealing conductor 61 is held inan electrically floating state. The sealing conductor 61 does not form acurrent path connected to the device region 62.

The sealing conductor 61 is formed in the shape of a stripe along theinsulation side walls 53A to 53D. In the embodiment, the sealingconductor 61 is formed in a quadrangular ring shape (specifically, arectangular ring shape) as seen in a plan view. Thus, the sealingconductor 61 defines the outer region 63 in a quadrangular ring shape(specifically, a rectangular ring shape) surrounding the device region62 as seen in a plan view.

Specifically, the sealing conductor 61 has a top end part at theinsulation principal surface 52 side, a bottom end part at thesemiconductor chip 41 side, and a wall part that extends in the form ofwalls between the top and bottom end parts. In the embodiment, the topend part of the sealing conductor 61 is formed at an interval from theinsulation principal surface 52 toward the semiconductor chip 41, and islocated in the insulation layer 51. In the embodiment, the top end partof the sealing conductor 61 is covered by the top insulation layer 56.The top end part of the sealing conductor 61 can be covered by one or aplurality of interlayer insulation layers 57. The top end part of thesealing conductor 61 can be exposed through the top insulation layer 56.The bottom end part of the sealing conductor 61 is formed at an intervalfrom the semiconductor chip 41 toward the top end part.

Thus, in the embodiment, the sealing conductor 61 is embedded in theinsulation layer 51 so as to be located at the semiconductor chip 41side of the plurality of low-potential terminals 11 and the plurality ofhigh-potential terminals 12. Moreover, in the insulation layer 51, thesealing conductor 61 faces, in the direction parallel to the insulationprincipal surface 52, the first functional device 45 (plurality oftransformers 21), the first low-potential wirings 31, the secondlow-potential wirings 32, the first high-potential wirings 33, thesecond high-potential wirings 34, and the dummy pattern 85. In theinsulation layer 51, the sealing conductor 61 can face, in the directionparallel to the insulation principal surface 52, part of the secondfunctional device 60.

The sealing conductor 61 includes a plurality of sealing plug conductors64 and one or a plurality of (in the embodiment, a plurality of) sealingvia conductors 65. Any number of sealing via conductors 65 may beprovided. Of the plurality of sealing plug conductors 64, the topsealing plug conductor 64 constitutes the top end part of the sealingconductor 61. The plurality of sealing via conductors 65 constitute thebottom end part of the sealing conductor 61. Preferably, the sealingplug conductors 64 and the sealing via conductors 65 are formed of thesame conductive material as the low-potential coil 22. That is,preferably, like the low-potential coil 22 and the like, the sealingplug conductors 64 and the sealing via conductors 65 each include abarrier layer and a body layer.

The plurality of sealing plug conductors 64 are embedded in theplurality of interlayer insulation layers 57 respectively, and are eachformed in a quadrangular ring shape (specifically, a rectangular ringshape) surrounding the device region 62. The plurality of sealing plugconductors 64 are stacked together from the bottom insulation layer 55to the top insulation layer 56 so as to be connected together. Thenumber of layers stacked in the plurality of sealing plug conductors 64is equal to the number of layers in the plurality of interlayerinsulation layers 57. Needless to say, one or a plurality of sealingplug conductors 64 may be formed that penetrates a plurality ofinterlayer insulation layers 57.

So long as a set of a plurality of sealing plug conductor 64 constitutesone ring-shaped sealing conductor 61, not all the sealing plugconductors 64 need be formed in a ring shape. For example, at least oneof the plurality of sealing plug conductors 64 can be formed so as tohave ends. Or at least one of the plurality of sealing plug conductors64 may be divided into a plurality of strip-shaped portions with ends.However, with consideration given to the risk of moisture entry andcrack development into the device region 62, preferably, the pluralityof sealing plug conductors 64 are formed so as to have no ends (in aring shape).

The plurality of sealing via conductors 65 are formed in the bottominsulation layer 55, in a region between the semiconductor chip 41 andthe sealing plug conductors 64. The plurality of sealing via conductors65 are formed at an interval from the semiconductor chip 41, and areconnected to the sealing plug conductors 64. The plurality of sealingvia conductors 65 have a plane area smaller than the plane area of thesealing plug conductors 64. In a case where a single sealing viaconductor 65 is formed, the single sealing via conductors 65 can have aplane area larger than the plane area of the sealing plug conductors 64.

The sealing conductor 61 can have a width of 0.1 μm or more but 10 μm orless. Preferably, the sealing conductor 61 has a width of 1 μm or morebut 5 μm or less. The width of the sealing conductor 61 is defined byits width in the direction orthogonal to the direction in which itextends.

Referring to FIGS. 7 and 8 , the semiconductor device 5 further includesa separation structure 130 that is interposed between the semiconductorchip 41 and the sealing conductor 61 and that electrically isolates thesealing conductor 61 from the semiconductor chip 41. Preferably, theseparation structure 130 includes an insulator. In the embodiment, theseparation structure 130 is a field insulation film 131 formed on thefirst principal surface 42 of the semiconductor chip 41.

The field insulation film 131 includes at least one of an oxide film(silicon oxide film) and a nitride film (silicon nitride film).Preferably, the field insulation film 131 is a LOCOS (local oxidation ofsilicon) film as one example of an oxide film that is formed throughoxidation of the first principal surface 42 of the semiconductor chip41. The field insulation film 131 can have any thickness so long as itcan insulate between the semiconductor chip 41 and the sealing conductor61. The field insulation film 131 can have a thickness of 0.1 μm or morebut 5 μm or less.

The separation structure 130 is formed on the first principal surface 42of the semiconductor chip 41, and extends in the shape of a stripe alongthe sealing conductor 61 as seen in a plan view. In the embodiment, theseparation structure 130 is formed in a quadrangular ring shape(specifically, a rectangular ring shape) as seen in a plan view. Theseparation structure 130 has a connection portion 132 to which thebottom end part of the sealing conductor 61 (i.e., the sealing viaconductors 65) is connected. The connection portion 132 can form ananchor portion into which the bottom end part of the sealing conductor61 (i.e., the sealing via conductors 65) is anchored toward thesemiconductor chip 41. Needless to say, the connection portion 132 canbe formed to be flush with the principal surface of the separationstructure 130.

The separation structure 130 includes an inner end part 130A at thedevice region 62 side, an outer end part 130B at the outer region 63side, and a main body part 130C between the inner and outer end parts130A and 130B. As seen in a plan view, the inner end part 130A definesthe region where the second functional device 60 is formed (i.e., thedevice region 62). The inner end part 130A can be formed integrally withan insulation film (not illustrated) formed on the first principalsurface 42 of the semiconductor chip 41.

The outer end part 130B is exposed on the chip side walls 44A to 44D ofthe semiconductor chip 41, and is continuous with the chip side walls44A to 44D of the semiconductor chip 41. More specifically, the outerend part 130B is formed so as to be flush with the chip side walls 44Ato 44D of the semiconductor chip 41. The outer end part 130B constitutesa polished surface between, to be flush with, the chip side walls 44A to44D of the semiconductor chip 41 and the insulation side walls 53A to53D of the insulation layer 51. Needless to say, an embodiment is alsopossible where the outer end part 130B is formed within the firstprincipal surface 42 at intervals from the chip side walls 44A to 44D.

The main body part 130C has a flat surface that extends substantiallyparallel to the first principal surface 42 of the semiconductor chip 41.The main body part 130C has the connection portion 132 to which thebottom end part of the sealing conductor 61 (i.e., the sealing viaconductors 65) is connected. The connection portion 132 is formed in themain body part 130C, at intervals from the inner and outer end parts130A and 130B. The separation structure 130 can be implemented in manyways other than in the form of a field insulation film 131.

Referring to FIG. 7 , the semiconductor device 5 further includes aninorganic insulation layer 140 formed on the insulation principalsurface 52 of the insulation layer 51 so as to cover the sealingconductor 61. The inorganic insulation layer 140 can be called apassivation layer. The inorganic insulation layer 140 protects theinsulation layer 51 and the semiconductor chip 41 from above theinsulation principal surface 52.

In the embodiment, the inorganic insulation layer 140 has a stackedstructure composed of a first inorganic insulation layer 141 and asecond inorganic insulation layer 142. The first inorganic insulationlayer 141 can contain silicon oxide. Preferably, the first inorganicinsulation layer 141 contains USG (undoped silicate glass), which isundoped silicon oxide. The first inorganic insulation layer 141 can havea thickness of nm or more but 5000 nm or less. The second inorganicinsulation layer 142 can contain silicon nitride. The second inorganicinsulation layer 142 can have a thickness of 500 nm or more but 5000 nmor less. Increasing the total thickness of the inorganic insulationlayer 140 helps increase the dielectric strength voltage above thehigh-potential coils 23.

In a configuration where the first inorganic insulation layer 141 ismade of USG and the second inorganic insulation layer 142 is made ofsilicon nitride, USG has the higher dielectric breakdown voltage (V/cm)than silicon nitride. In view of this, when thickening the inorganicinsulation layer 140, it is preferable to form the first inorganicinsulation layer 141 thicker than the second inorganic insulation layer142.

The first inorganic insulation layer 141 can contain at least one ofBPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicateglass) as examples of silicon oxide. In that case, however, since thesilicon oxide contains a dopant (boron or phosphorus), for an increaseddielectric strength voltage above the high-potential coils 23, it isparticularly preferable to form the first inorganic insulation layer 141of USG. Needless to say, the inorganic insulation layer 140 can have asingle-layer structure composed of either the first or second inorganicinsulation layer 141 or 142.

The inorganic insulation layer 140 covers the entire area of the sealingconductor 61, and has a plurality of low-potential pad openings 143 anda plurality of high-potential pad openings 144 that are formed in aregion outside the sealing conductor 61. The plurality of low-potentialpad openings 143 expose the plurality of low-potential terminals 11respectively. The plurality of high-potential pad openings 144 exposethe plurality of high-potential terminals 12 respectively. The inorganicinsulation layer 140 can have overlap parts that overlap circumferentialedge parts of the low-potential terminals 11. The inorganic insulationlayer 140 can have overlap parts that overlap circumferential edge partsof the high-potential terminals 12.

The semiconductor device 5 further includes an organic insulation layer145 that is formed on the inorganic insulation layer 140. The organicinsulation layer 145 can contain photosensitive resin. The organicinsulation layer 145 can contain at least one of polyimide, polyamide,and polybenzoxazole. In the embodiment, the organic insulation layer 145contains polyimide. The organic insulation layer 145 can have athickness of 1 μm or more but 50 μm or less.

Preferably, the organic insulation layer 145 has a thickness larger thanthe total thickness of the inorganic insulation layer 140. Moreover,preferably, the inorganic and organic insulation layers 140 and 145together have a total thickness larger than the distance D2 between thelow- and high-potential coils 22 and 23. In that case, preferably, theinorganic insulation layer 140 has a total thickness of 2 μm or more but10 μm or less. Preferably, the organic insulation layer 145 has athickness of 5 μm or more but 50 μm or less. Such structures helpsuppress an increase in the thicknesses of the inorganic and organicinsulation layers 140 and 145 while appropriately increasing thedielectric strength voltage above the high-potential coil 23 owing tothe stacked film of the inorganic and organic insulation layers 140 and145.

The organic insulation layer 145 includes a first part 146 that covers alow-potential side region and a second part 147 that covers ahigh-potential side region. The first part 146 covers the sealingconductor 61 across the inorganic insulation layer 140. The first part146 has a plurality of low-potential terminal openings 148 through whichthe plurality of low-potential terminals 11 (low-potential pad openings143) are respectively exposed in a region outside the sealing conductor61. The first part 146 can have overlapping parts that overlapcircumferential edges (overlap parts) of the low-potential pad openings143.

The second part 147 is formed at an interval from the first part 146,and exposes the inorganic insulation layer 140 between the first andsecond parts 146 and 147. The second part 147 has a plurality ofhigh-potential terminal openings 149 through which the plurality ofhigh-potential terminals 12 (high-potential pad openings 144) arerespectively exposed. The second part 147 can have overlap parts thatoverlap circumferential edges (overlap parts) of the high-potential padopenings 144.

The second part 147 covers the transformers 21A to 21D and the dummypattern 85 together. Specifically, the second part 147 covers theplurality of high-potential coils 23, the plurality of high-potentialterminals 12, a first high-potential dummy pattern 87, a secondhigh-potential dummy pattern 88, and a floating dummy pattern 121together.

The present invention can be implemented in any other embodiments. Theembodiment described above deals with an example where a firstfunctional device 45 and a second functional device 60 are formed. Anembodiment is however also possible that only has a second functionaldevice 60, with no first functional device 45. In that case, the dummypattern 85 may be omitted. This structure provides, with respect to thesecond functional device 60, effects similar to those mentioned inconnection with the first embodiment (except those associated with thedummy pattern 85).

That is, in a case where a voltage is applied to the second functionaldevice 60 via the low- and high-potential terminals 11 and 12, it ispossible suppress unnecessary conduction between the high-potentialterminal 12 and the sealing conductor 61. Likewise, in a case where avoltage is applied to the second functional device 60 via the low- andhigh-potential terminals 11 and 12, it is possible suppress unnecessaryconduction between the low-potential terminal 11 and the sealingconductor 61.

The embodiment described above deals with an example where a secondfunctional device 60 is formed. The second functional device 60 howeveris not essential, and can be omitted.

The embodiment described above deals with an example where a dummypattern 85 is formed. The dummy pattern 85 however is not essential, andcan be omitted.

The embodiment described above deals with an example where the firstfunctional device 45 is of a multichannel type that includes a pluralityof transformers 21. It is however also possible to employ asingle-channel first functional device 45 that includes a singletransformer 21.

<Transformer Layout>

FIG. 9 is a plan view (top view) schematically showing one example oftransformer layout in a two-channel transformer chip 300 (correspondingto the semiconductor device 5 described previously). The transformerchip 300 shown there includes a first transformer 301, a secondtransformer 302, a third transformer 303, a fourth transformer 304, afirst guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 tob8, pads c1 to c4, and pads d1 to d4.

In the transformer chip 300, the pads a1 and b1 are connected to oneterminal of the secondary coil L1 s of the first transformer 301, andthe pads c1 and d1 are connected to the other terminal of that secondarycoil L1 s. The pads a2 and b2 are connected to one terminal of thesecondary coil L2 s of the second transformer 302, and the pads c1 andd1 are connected to the other terminal of that secondary coil L2 s.

Moreover, the pads a3 and b3 are connected to one terminal of thesecondary coil L3 s of the third transformer 303, and the pads c2 and d2are connected to the other terminal of that secondary coil L3 s. Thepads a4 and b4 are connected to one terminal of the secondary coil L4 sof the fourth transformer 304, and the pads c2 and d2 are connected tothe other terminal of that secondary coil L4 s.

FIG. 9 does not show any of the primary coils of the first, second,third, and fourth transformers 301, 302, 303, and 304. The primary coilsbasically have structures similar to those of the secondary coils L1 sto L4 s respectively, and are disposed right below the secondary coilsL1 s to L4 s, respectively, so as to face them.

Specifically, the pads a5 and b5 are connected to one terminal of theprimary coil of the first transformer 301, and the pads c3 and d3 areconnected to the other terminal of that primary coil. Likewise, the padsa6 and b6 are connected to one terminal of the primary coil of thesecond transformer 302, and the pads c3 and d3 are connected to theother terminal of that primary coil.

Likewise, the pads a7 and b7 are connected to one terminal of theprimary coil of the third transformer 303, and the pads c4 and d4 areconnected to the other terminal of that primary coil. Likewise, the padsa8 and b8 are connected to one terminal of the primary coil of thefourth transformer 304, and the pads c4 and d4 are connected to theother terminal of that primary coil.

The pads a5 to a8, the pads b5 to b8, the pads c3 and c4, and the padsd3 and d4 mentioned above are each led from inside the transformer chip300 to its surface across an unillustrated via.

Of the plurality of pads mentioned above, the pads a1 to a8 eachcorrespond to a first current feed pad, and the pads b1 to b8 eachcorrespond to a first voltage measurement pad; the pads c1 to c4 eachcorrespond to a second current feed pad, and the pads d1 to d4 eachcorrespond to a second voltage measurement pad.

Thus, the transformer chip 300 of this configuration example permits,during its defect inspection, accurate measurement of the seriesresistance component across each coil. It is thus possible not only toreject defective products with a broken wire in a coil but also toappropriately reject defective products with an abnormal resistancevalue in a coil (e.g., a midway short circuit between coils), and henceto prevent defective products from being distributed in the market.

For a transformer chip 300 that has passed the defect inspectionmentioned above, the plurality of pads described above can be used forconnection with a primary-side chip and a secondary-side chip (e.g., thecontroller chip 210 and the driver chip 220 described previously).

Specifically, the pads a1 and b1, the pads a2 and b2, the pads a3 andb3, and the pads a4 and b4 can each be connected to one of the signalinput and output terminals of the secondary-side chip; the pads c1 andd1 and the pads c2 and d2 can each be connected to a common voltageapplication terminal (GND2) of the secondary-side chip.

On the other hand, the pads a5 and b5, the pads a6 and b6, the pads a7and b7, and the pads a8 and b8 can each be connected to one of thesignal input and output terminals of the primary-side chip; the pads c3and d3 and the pads c4 and d4 can each be connected to a common voltageapplication terminal (GND1) of the primary-side chip.

Here, as shown in FIG. 9 , the first to fourth transformers 301 to 304are so arranged as to be coupled for each signal transmission direction.In terms of what is shown in the diagram, for example, the first andsecond transformers 301 and 302, which transmit a signal from theprimary-side chip to the secondary-side chip, are coupled into a firstpair by the first guard ring 305. Likewise, for example, the third andfourth transformers 303 and 302, which transmit a signal from thesecondary-side chip to the primary-side chip, are coupled into a secondpair by the second guard ring 306.

Such coupling is intended, in a structure where the primary andsecondary coils of each of the first to fourth transformers 301 to 304are formed so as to be stacked on each other in the up-down direction ofthe substrate, to obtain a desired withstand voltage between the primaryand secondary coils. The first and second guard rings 305 and 306 arehowever not essential elements.

The first and second guard rings 305 and 306 can be connected via padse1 and e2, respectively, to a low-impedance wiring such as a groundedterminal.

In the transformer chip 300, the pads c1 and d1 are shared between thesecondary coils L1 s and L2 s. The pads c2 and d2 are shared between thesecondary coils L3 s and L4 s. The pads c3 and d3 are shared between theprimary coils L1 p and L2 p. The pads c4 and d4 are shared between theprimary coils that correspond to them respectively. This configurationhelps reduce the number of pads and helps make the transformer chip 300compact.

Moreover, as shown in FIG. 9 , the primary and secondary coils of thefirst to fourth transformers 301 to 304 are preferably each wound in arectangular shape (or, with the corners rounded, in a running-trackshape) as seen in a plan view of the transformer chip 300. Thisconfiguration helps increase the area over which the primary andsecondary coils overlap each other and helps enhance the transmissionefficiency across the transformers.

Needless to say, the illustrated transformer layout is merely anexample; any number of coils of any shape can be disposed in any layout,and pads can be disposed in any layout. Any of the chip structure,transformer layouts, etc. described above can be applied tosemiconductor devices in general that have a coil integrated in asemiconductor chip.

<Traction Inverter>

FIG. 10 is a diagram showing the basic configuration of a tractioninverter incorporated in an electric vehicle. The traction inverter 400of this configuration example is a kind of motor driving device thatconverts direct-current electric power supplied from an unillustratedvehicle-mounted battery into alternating-current electric power to drivea motor M. The traction inverter 400 includes an isolated gate driver 1,an ECU (electronic control unit) 2, and various discrete components (ahigh-side switch SWH, a low-side switch SWL, an npn-type bipolartransistor Q1, a pnp-type bipolar transistor Q2, resistors R1 to R3, andcapacitors C1 and C2).

Examples of electric vehicles (what is called xEVs) in which thetraction inverter 400 can be incorporated include BEVs (battery electricvehicles), HEVs (hybrid electric vehicles), PHEVs (plug-in hybridelectric vehicles)/PHVs (plug-in hybrid vehicles), and FCEVs (fuel cellelectric vehicles)/FCVs (fuel cell vehicles).

The isolated gate driver 1 is a semiconductor integrated circuit device(e.g., corresponding to the signal transmission device 200 in FIG. 1 )that, while isolating between a primary circuit system (VCC1-GND1)supplied with electric power from a direct-current voltage source E1 anda secondary circuit system (VCC2-GND2) that is supplied with electricpower from a direct-current voltage source E2, transmits a gate drivingsignal from the primary circuit system to the secondary circuit system.

The isolated gate driver 1 has, as means for establishing electricalconnection with outside it, a plurality of external terminals (of whichsome are shown in the diagram, namely a VCC1 terminal, an IN terminal,an FLT1 terminal, an FLT2 terminal, a GND1 terminal, a VCC2 terminal, anOUT terminal, a CLAMP terminal, a PROOUT terminal, and a GND2 terminal).

The VCC1 terminal is the power terminal of the primary circuit system.The IN terminal is a control input terminal. The FLT1 and FLT2 terminalsare each a fault signal output terminal. The GND1 terminal is the groundterminal of the primary circuit system. The VCC2 terminal is the powerterminal of the secondary circuit system. The OUT terminal is an outputterminal. The CLAMP terminal is a mirror clamp terminal. The PROOUTterminal is a soft turn-off terminal. The GND2 terminal is the groundterminal of the secondary circuit system.

The internal configuration and the operation of the isolated gate driver1 will be described in detail later.

The ECU 2 serves as a means for comprehensive electrical control of anelectric vehicle, and engages in exchange of various signals (an inputsignal IN, external fault signals FLT1 and FLT2, etc.) with the isolatedgate driver 1.

The discrete components are interconnected as follows. The resistor R1is connected between the VCC1 terminal and the FLT1 terminal. Theresistor R2 is connected between the VCC1 terminal and the FLT2terminal. The resistor R3 is connected between the CLAMP terminal andthe PROOUT terminal. The capacitor C1 is connected between the VCC1terminal and the GND1 terminal. The capacitor C2 is connected betweenthe VCC2 terminal and the GND2 terminal.

The collector of the transistor Q1 is connected to the VCC2 terminal.The emitters of the transistors Q1 and Q2 and the control terminal(e.g., gate) of the high-side switch SWH are all connected to the CLAMPterminal. The collector of the transistor Q2 is connected to the GND2terminal. The bases of the transistors Q1 and Q2 are both connected tothe OUT terminal.

The high-side and low-side switches SWH and SWL are connected,respectively, between an application terminal for a first motor drivingvoltage VD1 and an input terminal of the motor M corresponding to therelevant phase (specifically, one end of the motor coil of that phase)and between the input terminal of the motor M corresponding to therelevant phase and an application terminal for a second motor drivingvoltage VD2 (<VD1). As these switches SWH and SWL are turned on and off,they control the supply of a motor driving current, thus constituting ahalf-bridge output stage.

In the traction inverter 400 of this configuration example, thehigh-side and low-side switches SWH and SWL are implemented withinsulated-gate bipolar transistors (IGBTs). This, however, is not meantto limit the configuration of the half-bridge output stage: instead,they may be implemented with MOS (metal-oxide-semiconductor)field-effect transistors using a SiC (silicon carbide) semiconductor orMOS field-effect transistors using a Si semiconductor. In particular,MOS field-effect transistors using a SiC, for their low powerconsumption and high heat resistance as compared with MOS field-effecttransistors using a Si semiconductor, are suitable for use on electricvehicles.

For the sake of convenience, the diagram only shows the half-bridgeoutput stage corresponding to one phase and the isolated gate driver 1connected to the high-side switch SWH. In reality, an isolated gatedriver 1 is connected to each of the high-side and low-side switches SWHand SWL constituting the half-bridge output stage of each phase.Accordingly, in a case where the motor M is a three-phase AC(alternating-current) motor, there are provided half-bridge outputstages for three phases, and these require a total of six isolated gatedrivers 1.

<Isolated Gate Driver (Basic Configuration)>

With reference still to FIG. 10 . The isolated gate driver 1 will bedescribed in detail. The isolated gate driver 1 has a firstsemiconductor chip 410, a second semiconductor chip 420, and a thirdsemiconductor chip 430 sealed in a single package.

The first semiconductor chip 410 is a controller chip that hasintegrated in it a controller that is driven by being supplied with asupply voltage VCC1 (e.g., 5 V or 3.3 V relative to GND1) from thedirect-current voltage source E1 to generate switch control signals S1and S2 based on an input signal IN. The first semiconductor chip 410 hasthe following main functions: generating the switch control signals S1and S2; generating external fault signals FLT1 and FLT2; and performingUVLO (undervoltage lock-out). The first semiconductor chip 410 can bedesigned to have an appropriate withstand voltage (e.g., 7 [V]) withconsideration given to the supply voltage VCC1 (relative to GND1).

The second semiconductor chip 420 is a driver chip that has integratedin it a driver that is driven by being supplied with a supply voltageVCC2 (10 to 30 V relative to GND2) from the direct-current voltagesource E2 to control the driving of the high-side switch SWH, of whichone terminal is fed with a voltage as high as several hundred volts,based on the switch control signals S1 and S2 fed from the firstsemiconductor chip 410 via the third semiconductor chip 430. The secondsemiconductor chip 420 has the following main functions: generating anoutput signal OUT; generating internal fault signals S3 and S4; andperforming UVLO. The second semiconductor chip 420 can be designed tohave an appropriate withstand voltage (e.g., 40 [V]) with considerationgiven to the supply voltage VCC2 (relative to GND2).

The third semiconductor chip 430 is a transformer chip that hasintegrated in it a transformer that, while isolating between the firstand second semiconductor chips 410 and 420 on a direct-current basis,exchanges the switch control signals S1 and S2 and the internal faultsignals S3 and S4.

As described above, the isolated gate driver 1 of this configurationexample has, separately from the first semiconductor chip 410 having acontroller integrated in it and the second semiconductor chip 420 havinga driver integrated in it, the transformer chip 430 incorporating atransformer alone, and these three chips are sealed in a single package.

With this configuration, the first and second semiconductor chips 410and 420 can each be formed by a common low-withstand-voltage process(with a withstand voltage of several volts to several tens of volts).This eliminates the need for a dedicated high-withstand-voltage process(with a withstand voltage of several kilovolts), and helps reducemanufacturing costs.

Moreover, the first and second semiconductor chips 410 and 420 can eachbe fabricated by a time-proven existing process. This eliminates theneed for conducting reliability tests anew, and contributes to ashortened development period and reduced development costs.

Next, the internal configuration of each of the first, second, and thirdsemiconductor chips 410, 420, and 430 incorporated in the isolated gatedriver 1 will be described in detail one by one.

The first semiconductor chip 410 includes a first transmitter 411, asecond transmitter 412, a first receiver 413, a second receiver 414, alogic circuit 415, a first UVLO circuit 416, and N-channel MOSfield-effect transistors Na and Nb.

The second semiconductor chip 420 includes a third receiver 421, afourth receiver 422, a third transmitter 423, a fourth transmitter 424,a logic circuit 425, a driver 426, a second UVLO circuit 427, aP-channel MOS field-effect transistor P1, N-channel MOS field-effecttransistors N1 to N3, and an SR flip-flop FF.

The third semiconductor chip 430 includes a first transformer 431, asecond transformer 432, a third transformer 433, and a fourthtransformer 434.

The first transmitter 411 transmits the switch control signal S1, whichis fed from the logic circuit 415, to the third receiver 421 via thefirst transformer 431.

The second transmitter 412 transmits the switch control signal S2, whichis fed from the logic circuit 415, to the fourth receiver 422 via thesecond transformer 432.

The first receiver 413 receives the internal fault signal S3, which isfed from the third transmitter 423 via the third transformer 433, todeliver the internal fault signal S3 to the logic circuit 415.

The second receiver 414 receives the internal fault signal S4, which isfed from the fourth transmitter 424 via the fourth transformer 434, todeliver the internal fault signal S4 to the logic circuit 415.

The logic circuit 415 exchanges various signals (the input signal IN andthe external fault signals FLT1 and FLT2) with the ECU 2, and exchangesvarious signals (S1 to S4) with the second semiconductor chip 420 byusing the first transmitter 411, the second transmitter 412, the firstreceiver 413, and the second receiver 414.

If the input signal IN is at high level, the logic circuit 415 generatesa pulse in the switch control signal S1 to turn the output signal OUT tohigh level; by contrast, if the input signal IN is at low level, thelogic circuit 415 generates a pulse in the switch control signal S2 toturn the output signal OUT to low level. For example, the logic circuit415 raises a pulse in the switch control signal S1 by detecting apositive edge (a rising edge from low level to high level) in the inputsignal IN, and raises a pulse in the switch control signal S2 bydetecting a negative edge (a falling edge from high level to low level)in the input signal IN.

Moreover, according to the state of the isolated gate driver 1, thelogic circuit 415 turns the transistors Na and Nb on and off to switchthe logic levels of the external fault signals FLT1 and FLT2.

The drains of the transistors Na and Nb are connected to the FLT1 andFLT2 terminals respectively. The sources of the transistors Na and Nbare both connected to the ground terminal (i.e., the GND1 terminal) ofthe primary circuit system. The gates of the transistors Na and Nb areboth connected to the logic circuit 415.

For example, so long as the isolated gate driver 1 has no fault, thetransistors Na and Nb are both off, so that the FLT1 and FLT2 are bothin a high-impedance state (a state pulled up by the resistor R1). Inthis state, the external fault signals FLT1 and FLT2 are both at highlevel (=VCC1). By contrast, if the isolated gate driver 1 has somefault, at least one of the transistors Na and Nb is on, so that at leastone of the FLT1 and FLT2 is in a state short-circuited to the ground. Inthis state, at least one of the external fault signals FLT1 and FLT2 isat low level (=GND1). With this configuration, the ECU 2 can, bymonitoring the external fault signals FLT1 and FLT2, grasp the state ofthe isolated gate driver 1. This function, fault output function, willbe described in detail later.

The first UVLO circuit 416 monitors whether the supply voltage VCC1 isin an undervoltage state and delivers the monitoring result to the logiccircuit 415.

The third receiver 421 receives the switch control signal S1, which isfed from the first transmitter 411 via the first transformer 431, todeliver the switch control signal S1 to the set input terminal (S) ofthe SR flip-flop FF.

The fourth receiver 422 receives the switch control signal S2, which isfed from the second transmitter 412 via the second transformer 432, todeliver the switch control signal S2 to the reset input terminal (R) ofthe SR flip-flop FF.

The third transmitter 423 transmits the internal fault signal S3, whichis fed from the logic circuit 425, to the first receiver 413 via thethird transformer 433.

The fourth transmitter 424 transmits the internal fault signal S4, whichis fed from the logic circuit 425, to the second receiver 414 via thefourth transformer 434.

Triggered by a pulse edge in the switch control signal S1 fed to its setinput terminal (S), the SR flip-flop FF sets the logic level at itsoutput terminal (Q) to high level. Triggered by a pulse edge in theswitch control signal S2 fed to its reset input terminal (R), the SRflip-flop FF resets the logic level at its output terminal (Q) to lowlevel. Thus, the output signal fed from the SR flip-flop FF to the logiccircuit 425 is a pulse signal that has the same logic level as the inputsignal IN fed from the ECU 2 to the logic circuit 415.

Based on the output signal of the SR flip-flop FF, the logic circuit 425generates a driving signal for the driver 426. If the second UVLOcircuit 427 detects an undervoltage fault, the logic circuit 425 sends acorresponding notification directly to the driver 426 and also, by usingthe internal fault signal S3, to the logic circuit 415. With thisconfiguration, even if the second semiconductor chip 420 has anundervoltage fault, the driver 426 can promptly perform protectionoperation, and the logic circuit 415 can perform fault output to the ECU2.

Though not specifically shown in the diagram, the second semiconductorchip 420 may include any fault detector other than the second UVLOcircuit 427 (such as an overvoltage detector OVP [overvoltageprotection], a short-circuit detector SCP [short-circuit protection], oran overtemperature detector OTP [overtemperature protection]). In thatcase, if any fault is detected in the second semiconductor chip 420, asin the case described above, protection operation can be performed forthe driver 426 and fault output can be performed to the logic circuit415 (hence the ECU 2) by use of the internal fault signal S3.

As will be described in detail later, the second semiconductor chip 420may include a non-volatile memory for use as registers. In that case, ifan error is detected in the data stored in the non-volatile memory,fault output may be performed to the logic circuit 415 (hence the ECU 2)by use of, for example, the internal fault signal S4 provided separatelyfrom the internal fault signal S3 mentioned above.

The source of the transistor P1 is connected to the VCC2 terminal. Thedrains of the transistors P1 and N1 are both connected to the OUTterminal. The drain of the transistor N2 is connected to the CLAMPterminal. The drain of the transistor N3 is connected to the PROOUTterminal. The sources of the transistors N1 to N3 are all connected tothe GND2 terminal. The gates of the transistors P1 and N1 to N3 are allconnected to the driver 426.

The driver 426 turns on and off the transistors P1 and N1 based on adriving signal fed from the logic circuit 425 to output the outputsignal OUT from the connection node between the transistors P1 and N1.The output signal OUT is fed via a driving circuit constituted by thetransistors Q1 and Q2 to the high-side switch SWH. In the drivingcircuit just mentioned, the rising/falling time (slew rate) of theoutput signal OUT is set such that the output signal OUT has thecapacity to drive the high-side switch SWH. Here, when the output signalOUT is at high level, the high-side switch SWH is on; when the outputsignal OUT is at low level, the high-side switch SWH is off.

The driver 426 has a function (active mirror clamp function) of, inresponse to the voltage level of the output signal OUT (relative toGND2) turning to low level, turning on the transistor N2 so as to drawelectric charge (mirror current) from the gate of the high-side switchSWH via the CLAMP terminal. With this configuration, when the high-sideswitch SWH is turned off, it is possible to promptly drop the gatepotential of the high-side switch SWH to low level via the transistor N2regardless of the slew rate set by the driving circuit mentioned above.

The driver 426 also has a function (soft turn-on function) of, onrecognizing the need for protection operation based on a fault detectionsignal fed from the logic circuit 425, turning the transistors P1, N1,and N2 all off and the transistor N3 on. Such switching permits electriccharge to be drawn more gently from the gate of the high-side switch SWHvia the resistor R3 during protection operation than during normaloperation. This configuration helps avoid an instantaneous break of themotor current during protection operation, and thus helps suppress asurge ascribable to a back electromotive force in the motor coil. Thefalling time during protection operation can be adjusted as desired byappropriately selecting the resistance value of the resistor R3.

The second UVLO circuit 427 monitors whether the supply voltage VCC2 isin an undervoltage state and delivers the monitoring result to the logiccircuit 425.

The first transformer 431 is a direct-current isolation element fortransmitting the switch control signal S1 from the first semiconductorchip 410 to the second semiconductor chip 420.

The second transformer 432 is a direct-current isolation element fortransmitting the switch control signal S2 from the first semiconductorchip 410 to the second semiconductor chip 420.

The third transformer 433 is a direct-current isolation element fortransmitting the internal fault signal S3 from the second semiconductorchip 420 to the first semiconductor chip 410.

The fourth transformer 434 is a direct-current isolation element fortransmitting the internal fault signal S4 from the second semiconductorchip 420 to the first semiconductor chip 410.

With this configuration where not only the switch control signals S1 andS2 but also the internal fault signals S3 and S4 are exchanged betweenthe first and second semiconductor chips 410 and 420, it is possible notonly to turn on and off the high-side switch SWH but also to carry outvarious fault detection functions appropriately.

Here is a review of the different functions of the isolated gate driver1 of this configuration example.

[UVLO1 (Controller-Side Undervoltage-Induced Malfunctioning PreventionFunction)]

If the supply voltage VCC1 becomes equal to or lower than apredetermined low-side threshold voltage V_(UVLO1L), the isolated gatedriver 1 turns off the high-side switch SWH and keeps the FLT1 terminalat low level. If the supply voltage VCC1 becomes equal to or higher thana predetermined high-side threshold voltage V_(UVLO1H), the isolatedgate driver 1 starts normal operation and keeps the FLT1 terminal in ahigh-impedance state (at high level).

[UVLO2 (Driver-Side Undervoltage-Induced Malfunctioning PreventionFunction)]

If the supply voltage VCC2 becomes equal to or lower than apredetermined low-side threshold voltage V_(UVLO2L), the isolated gatedriver 1 turns off the high-side switch SWH and keeps the FLT1 terminalat low level. If the supply voltage VCC2 becomes equal to or higher thana predetermined high-side threshold voltage V_(UVLO2H), the isolatedgate driver 1 starts normal operation and keeps the FLT1 terminal in ahigh-impedance state (at high level).

[Soft Turn-Off During Protection Operation]

When forcibly turning off the high-side switch SWH, the isolated gatedriver 1 turns the PROOUT terminal to low level and brings the OUTterminal into a high-impedance state. This control permits the high-sideswitch SWH to be turned off slowly. The slew rate during its turning-offcan be adjusted as desired by appropriately selecting the resistancevalue of the externally connected resistor R3.

[Active Mirror Clamp]

When the gate potential of the high-side switch SWH becomes equal to orlower than a predetermined threshold voltage V_(AMC), the isolated gatedriver 1 turns the CLAMP terminal to low level. This control permitsreliable turning-off of the high-side switch SWH.

<A Study on Set Size and Cost Reduction>

In the traction inverter 400, optimizing the switching characteristicsof a switching element (e.g., the high-side switch SWH) implemented withan IGBT or the like and the operating threshold values of a faultdetector (such as an overvoltage detector OVP, short-circuit detectorSCP, or overtemperature detector OTP) will lead to reducing safetymargins against heating and destruction of the switching element. Thishelps reduce the chip size of the switching element and thus helpsachieve size reduction and cost reduction of sets.

Specifically, a characteristic of the isolated gate driver 1, forexample the driving speed of the gate driver (i.e., the slew rate), orthe detection threshold value or cancellation threshold value of a faultdetector, can be left adjustable as desired according to the individualvariation (manufacturing variation) of the switching element. Presentedbelow will be a novel embodiment devised to achieve that.

<Isolated Gate Driver (Embodiment)>

FIG. 11 is a diagram showing a novel embodiment of the isolated gatedriver 1. The isolated gate driver 1 according to this embodimentincludes a gate driver 441, a fault detector-controller 442, a register443, a control logic 444, a non-volatile memory 445, a memory controller446, and an interface 447. The following description assumes basicallythat these components are integrated in the second semiconductor chip420 (driver chip) in the isolated gate driver 1.

The gate driver 441 is a circuit block that corresponds to the driver426 in FIG. 10 . The gate driver 441 generates the output signal OUTbased on the driving signal fed from the logic circuit 425 (not shown inthe diagram), thereby to drive the gate of the high-side switch SWH. Thegate driver 441 is switched between an enabled and a disabled statebased on a fault detection signal fed from the fault detector-controller442. The characteristics of the gate driver 441 can be adjusted asdesired based on values (in the diagram, adjustment data D1) stored inthe register 443. The characteristics include, for example, the drivingspeed of the gate driver 441, that is, the rising/falling time (slewrate) of the output signal OUT.

The fault detector-controller 442 has combined functions as a faultdetector (such as an overvoltage detector OVP, short-circuit detectorSCP, or overtemperature detector OTP) that detects a fault elsewherethan in the non-volatile memory 445 and as a fault controller that feedsthe external fault signals FLT1 and FLT2 to the ECU 2 via the FLT1 andFLT2 terminals. For example, the FLT1 terminal corresponds to a firstexternal terminal for feeding out the result of fault detectionelsewhere than in the non-volatile memory 445, and the FLT2 terminalcorresponds to a second external terminal for feeding out the result oferror detection in the non-volatile memory 445. The characteristics ofthe fault detector-controller 442 can be adjusted as desired accordingto values (in the diagram, adjustment data D2) stored in the register443. The characteristics include, for example, the detection thresholdvalue or cancellation threshold value referred to in a check for afault.

Here, the fault detector-controller 442 includes, as its components, afault signal transmission mechanism for transmitting fault detectionresults from the second semiconductor chip 420 to the firstsemiconductor chip 410 (e.g., the first receiver 413, the secondreceiver 414, the third transmitter 423, the fourth transformer 434, thethird transformer 433, and the fourth transformer 434 in FIG. 10 ) and afault terminal control mechanism for controlling the FLT1 and FLT2terminals (e.g., the logic circuit 415 and the transistors Na and Nb inFIG. 10 ). Accordingly, the fault detector-controller 442 can beunderstood not to have all its components integrated in the secondsemiconductor chip 420 but have its components integrated in, in afashion distributed among, the first, second, and third semiconductorchips 410, 420, and 430.

The register 443 stores on a non-volatile basis the adjustment data readfrom the non-volatile memory 445 by the control logic 444 (i.e., in thediagram, the adjustment data D1 for the gate driver 441 and theadjustment data D2 for the fault detector-controller 442).

Every time the traction inverter 400 starts up (i.e., every time theisolated gate driver 1 starts receiving power), the control logic 444reads the adjustment data D1 and D2 from the non-volatile memory 445 andstores it in the register 443. Here, the control logic 444 has afunction of controlling the fault detector-controller 442 so as to keepthe gate driver 441 in a disabled state until the adjustment data D1 andD2 read from the non-volatile memory 445 completes being stored in theregister 443 (this will be described in detail later). Also, the controllogic 444 incorporates an error detection-correction circuit ECC (errorcheck and correct) that performs error detection and error correctionwith respect to the adjustment data D1 and D2 written to thenon-volatile memory 445 (this will be described in detail later).

The non-volatile memory 445 stores on a non-volatile basis theadjustment data for the isolated gate driver 1 (i.e., in the diagram,the adjustment data D1 for the gate driver 441 and the adjustment dataD2 for the fault detector-controller 442). While in this embodiment thenon-volatile memory 445 is incorporated in the isolated gate driver 1,it may instead be externally connected to the isolated gate driver 1 (aspecific example will be described later).

The memory controller 446 performs address control and the like withrespect to the non-volatile memory 445 when the non-volatile memory 445is accessed (e.g., to read or write the adjustment data D1 and D2) fromoutside the isolated gate driver 1 via the interface 447.

The interface 447 is a front end via which to access the non-volatilememory 445 from outside the isolated gate driver 1. The interface 447can be implemented with, for example, a two-line serial interfacecomplying with the I2C (inter-integrated circuit) standard that conductsbidirectional serial communication by use of a data signal SDA and aclock signal SCL.

With the isolated gate driver 1 according to this embodiment, by readingthe adjustment data D1 and D2 previously written to the non-volatilememory 445 and storing it in the register 443, it is possible tooptimize, based on the values stored in the register 443, thecharacteristics of each of the gate driver 441 and the faultdetector-controller 442. It is thus possible to reduce margins againstheating and destruction of the switching element (e.g. the high-sideswitch SWH), and thus to reduce the chip size of the switching elementand achieve size reduction and cost reduction of sets.

If, however, the gate driver 441 operates before the characteristics ofeach of the gate driver 441 and the fault detector-controller 442complete being set, that is, in other words, before the adjustment dataD1 and D2 completes being stored in the register 443, the switchingelement may be driven with inappropriate characteristics with noconsideration given to the individual (manufacturing) variation of theswitching element. In such a situation, the reduced safety margins canact adversely, leading to failure of the switching element.

Considering in particular that the register 443 is a kind of volatilememory, the above sequence of operation of reading the adjustment dataD1 and D2 from the non-volatile memory 445 and storing it in theregister 443 is repeated every time the traction inverter 400 is poweredup. Thus, the start-up sequence from powering-up to the start of gatedriving needs to be well designed.

<Start-up Sequence>

FIG. 12 is a flow chart showing the start-up sequence of the isolatedgate driver 1. The sequence proceeds as follows. At step #1, a set(i.e., the traction inverter 400) is powered up, so that the isolatedgate driver 1 starts to be supplied with the supply voltages VCC1 andVCC2.

At step #2, as the supply voltages VCC1 and VCC2 rise, the ULVO on theisolated gate driver 1 is cancelled. At this point, however, the readingof the adjustment data D1 and D2 from the non-volatile memory 445 hasnot been started yet and thus, naturally, its storing in the register443 and hence the adjustment of the characteristics of each of the gatedriver 441 and the fault detector-controller 442 has not been completed.Accordingly, the gate driver 441 is kept in a disabled state. The gatedriver 441 can be kept in a disabled state, for example, by keeping thefault detection signal fed from the fault detector-controller 442 to thegate driver 441 at a logic level indicating a fault being detected.

At step #3, the control logic 444 reads the adjustment data D1 and D2from the non-volatile memory 445 and stores it in the register 443.

At step #4, a check is made for completion of the storing of data in theregister 443 and hence completion of the adjustment of thecharacteristics of each of the gate driver 441 and the faultdetector-controller 442. If the check result is “yes”, the sequenceproceeds to step #5; if the check result is “no”, the sequence returnsto step #3 to continue, with the gate driver 441 kept in a disabledstate, the storing of data in the register 443.

If, at step #3, the storing of data in the register 443 is complete, thecharacteristics of each of the gate driver 441 and the faultdetector-controller 442 are optimized and thus the switching element(e.g., the high-side switch SWH) is now ready to be driven. Accordingly,if the sequence advances via step #4 resulting in “yes” to step #5, theisolated gate driver 1 becomes fault-released and the fault detectionsignal fed to the gate driver 441 is turned from the logic levelindicating a fault being detected to a logic level indicating no faultbeing detected.

As a result, at the subsequent step, #6, the gate driver 441 is releasedfrom the disabled state and the switching element starts to be drivenand controlled according to the input signal IN (normal operation).

As will be understood from the sequence of operation described above,the isolated gate driver 1 employs a start-up sequence that keeps thegate driver 441 in a disabled state until the characteristics of each ofthe gate driver 441 and the fault detector-controller 442 complete beingset, in other words, until the adjustment data D1 and D2 completes beingstored in the register 443.

With this configuration, even if the input signal IN is fed in from theECU 2 before the setting of the characteristics of each of the gatedriver 441 and the fault detector-controller 442, the switching elementis prevented from being driven with inappropriate characteristics withno consideration given to its individual (manufacturing) variation.Thus, operating the switching element with reduced safety margins isless likely to cause failure of the switching element.

<Examples of Implementation of a Non-Volatile Memory>

FIG. 13 is a diagram showing a first implementation example of thenon-volatile memory 445. The traction inverter 400 of the firstimplementation example is, as mentioned earlier, a kind of motor drivingdevice that controls the driving of a motor M, and includes threeisolated gate drivers 1H(u/v/w), three isolated gate drivers 1L(u/v/w),three high-side switches SWH(u/v/w), three low-side switches SWL(u/v/w),and an ECU 2.

The motor M is a three-phase motor that is driven to rotate according tothree-phase driving voltages U/V/W fed from half-bridge output stagescorresponding to three phases (U phase/V phase/W phase).

The isolated gate drivers 1H(u/v/w), while isolating between the ECU 2and the high-side switches SWH(u/v/w) respectively, generate high-sidegate drive signals (corresponding to the output pulse signal OUTmentioned above) according to the high-side gate control signals(corresponding to the input signal IN mentioned above) fed from the ECU2, and thereby drive the high-side switches SWH(u/v/w).

The isolated gate drivers 1L(u/v/w), while isolating between the ECU 2and the low-side switches SWL(u/v/w) respectively, generate low-sidegate drive signals according to the low-side gate control signals fedfrom the ECU 2, and thereby drive the low-side switches SWL(u/v/w).

The high-side switches SWH(u/v/w) are high-side power transistors thatconstitute half-bridge output stages of three phases (U phase/V phase/Wphase) respectively, and are externally connected to the switchconnection terminals T1 of the corresponding isolated gate drivers1H(u/v/w) (i.e., the OUT terminal, CLAMP terminal, PROOUT terminal, GND2terminal, etc. provided at the second semiconductor chip 420 side inFIG. 10 ) so that their gates are driven by the isolated gate drivers1H(u/v/w) respectively. The high-side switches SWH(u/v/w) are connectedbetween the power-system power supply terminal (an application terminalfor the first motor driving voltage VD1) and the input terminals of themotor M of the corresponding phases.

The low-side switches SWL(u/v/w) are low-side power transistors thatconstitute half-bridge output stages of three phases (U phase/V phase/Wphase) respectively, and are externally connected to the switchconnection terminals T1 of the corresponding isolated gate drivers1L(u/v/w) (i.e., the OUT terminal, CLAMP terminal, PROOUT terminal, GND2terminal, etc. provided at the second semiconductor chip 420 side inFIG. 10 ) so that their gates are driven by the isolated gate drivers1L(u/v/w) respectively. The low-side switches SWL(u/v/w) are connectedbetween the input terminals of the motor M of the corresponding phasesand the power-system ground terminal (an application terminal for thesecond motor driving voltage VD2).

While in the diagram the high-side and low-side switches SWH(u/v/w) andSWL(u/v/w) are implemented with IGBTs, as mentioned earlier they mayinstead be implemented with SiC-MOSFETs or Si-MOSFETs.

The ECU 2 drives via the isolated gate drivers 1H(u/v/w) and 1L(u/v/w)the high-side and low-side switches SWH(u/v/w) and SWL(u/v/w)respectively, and thereby controls the driving of the rotation of themotor M. The ECU 2 also has a function of monitoring the FLT1 and FLT2terminals of each of the isolated gate drivers 1H(u/v/w) and 1L(u/v/w)to achieve various kinds of safety control.

Here, the isolated gate driver 1 described previously can be usedsuitably as any of the isolated gate drivers 1H(u/v/w) and 1L(u/v/w).

In the traction inverter 400 of the first implementation example, theisolated gate drivers 1H(u/v/w) and 1L(u/v/w) each incorporate anon-volatile memory 445 for storing the corresponding adjustment data D1and D2. This configuration helps reduce the number of components of thetraction inverter 400.

FIG. 14 is a diagram showing a second implementation example of thenon-volatile memory 445. The traction inverter 400 of the secondimplementation example is based on the first implementation example(FIG. 13 ), a difference being that the non-volatile memory 445 isexternally connected.

In terms of what is shown in the diagram, specifically, in the tractioninverter 400 of the second implementation example, to memory connectionterminals T2 provided respectively at the secondary side (at the secondsemiconductor chip 420 side in FIG. 10 ) of the isolated gate drivers1H(u/v/w) and 1L(u/v/w), non-volatile memories 445 each having thecorresponding adjustment data D1 and D2 written to it are externallyconnected, on a one-memory-to-one-driver basis. With this configuration,the adjustment data D1 and D2 written to the non-volatile memory 445 onthe secondary side can be used to adjust the characteristics of each ofthe gate driver 441 and the fault detector-controller 442, which areprovided on the same, secondary, side. This eliminates the need forsignal transmission from the primary side to the secondary side, thatis, signal transmission from the first semiconductor chip 410 to thesecond semiconductor chip 420 via the third semiconductor chip 430. Thishelps simplify the circuit configuration of the isolated gate driver 1.

FIG. 15 is a diagram showing a third implementation example of thenon-volatile memory 445. The traction inverter 400 of the thirdimplementation example is based on the first implementation example(FIG. 13 ), a difference being that the non-volatile memory 445 isexternally connected.

In terms of what is shown in the diagram, specifically, in the tractioninverter 400 of the third implementation example, to memory connectionterminals T2 provided respectively at the primary side (at the firstsemiconductor chip 410 side in FIG. 10 ) of the isolated gate drivers1H(u/v/w) and 1L(u/v/w), a single non-volatile memory 445 having thecorresponding adjustment data D1 and D2 written to it is externallyconnected, on a one-memory-to-all-drivers basis. With thisconfiguration, it is possible to reduce the number of non-volatilememories 445 that are externally connected. It should however be notedthat this configuration still requires signal transmission from theprimary side to the secondary side, that is, signal transmission fromthe first semiconductor chip 410 to the second semiconductor chip 420via the third semiconductor chip 430.

<A Study on Deterioration of a Non-Volatile Memory>

As the non-volatile memory 445 deteriorates with time, the adjustmentdata D1 and D2 written to it may be lost. When this occurs, not all of aplurality of bits are lost at once but they are lost bit by bit. To stayprepared for that, it is preferable that the control logic 444 (ornon-volatile memory 445) be provided with an error detection-correctioncircuit ECC that performs error detection and error correction withrespect to the adjustment data D1 and D2 written to the non-volatilememory 445.

With the just-mentioned error detection-correction circuit ECCincorporated, if a one-bit error occurs in the adjustment data D1 and D2written to the non-volatile memory 445, it can be detected andcorrected. It is thus possible to properly perform characteristicsadjustment for the isolated gate driver 1 and continue the traveling ofthe electric vehicle without any problem. However, if a two-or-more-biterror occurs in the adjustment data D1 and D2 written to thenon-volatile memory 445, the error detection-correction circuit ECC canno longer correct them. This makes it impossible to properly performcharacteristics adjustment for the isolated gate driver 1 and continuesafe traveling of the electric vehicle.

In view of the above study, it is preferable to switch the fault outputfrom the isolated gate driver 1 according to whether the adjustment dataD1 and D2 has a one-bit error or a two-or-more-bit error. Presentedbelow will be examples of operation for appropriate fault output.

<Fault Output>

FIG. 16 is a table showing a first operation example of fault output,showing the error detection result with respect to the non-volatilememory 445, the enabled/disabled state of the gate driver 441, and theoutput states at the FLT1 and FLT2 terminals respectively. Errordetection with respect to the non-volatile memory 445 is carried outchiefly by the error detection-correction circuit ECC. Enabled/disabledstate switching for the gate driver 441 and fault output via the FLT1and FLT2 terminals are carried out chiefly by the faultdetector-controller 442.

As shown at line 1, when the adjustment data D1 and D2 written to thenon-volatile memory 445 is normal, the gate driver 441 performs normaloperation. In this case, the FLT1 and FLT2 terminals are both in ahigh-impedance state, and thus the external fault signals FLT1 and FLT2delivered to the ECU 2 are, by being pulled-up by the resistors R1 andR2, at high level (i.e., the logic level indicating normal condition).

As shown at line 2, if a one-bit error is detected in the adjustmentdata D1 and D2 written to the non-volatile memory 445, the FLT2 terminalis kept at low level (the logic level indicating an error beingdetected) and the gate driver 441 continues normal operation. The FLT1terminal remains in a high-impedance state. In this way, a one-bit errorcan be detected and corrected by the error detection-correction circuitECC, and thus the normal operation of the gate driver 441, and hence thetraveling of the electric vehicle, can be continued with no problem.

Even if a one-bit error is detected in the adjustment data D1 and D2,characteristics adjustment for the isolated gate driver 1 can beperformed properly; thus fault output for the ECU 2 (i.e., output of alow-level external fault signal FLT2) does not necessarily have to beperformed. Even so, by performing such fault output in anticipation ofan upcoming error in another bit, it is possible to previously notifythe electric vehicle's driver of the likelihood of a breakdown. It isthus possible to prevent the electric vehicle from breaking downsuddenly, with no previous sign, on occurrence of a two-bit error.

As shown at line 3, if a two-or-more-bit error is detected in theadjustment data D1 and D2 written to the non-volatile memory 445, theFLT1 and FLT2 terminals are both kept at low level and the gate driver441 is forcibly stopped. In this way, if a two-or-more-bit error occurs,it is impossible to correct the adjustment data D1 and D2 and thus toperform characteristics adjustment for the isolated gate driver 1properly. It is therefore of the highest priority to forcibly stop thegate driver 441 to ensure the safety of the electric vehicle.

Moreover, by dropping the external fault signal FLT1 to low level, it ispossible to promptly notify the ECU 2 of the occurrence of some seriousfault in the isolated gate driver 1 or the high-side switch SWH (here, atwo-or-more-bit error in the non-volatile memory 445 and the resultingforcible stop of the gate driver 441).

FIG. 17 is a table showing a second operation example of fault outputand, like FIG. 16 referred to previously, shows the error detectionresult with respect to the non-volatile memory 445, the enabled/disabledstate of the gate driver 441, and the output states at the FLT1 and FLT2terminals respectively.

The second operation example shown in the diagram is basically similarto the first operation example (FIG. 16 ) described previously, the onlydifference being that, if a two-or-more-bit error is detected in theadjustment data D1 and D2 written to the non-volatile memory 445, theFLT2 terminal is kept in a high-impedance state. In this way, ondetection of a two-or-more-bit error, the FLT1 terminal is used toperform fault output for the ECU 2; thus, the output state at the FLT2terminal does not matter.

FIG. 18 is a table showing a third operation example of fault output,and shows the error detection result with respect to the non-volatilememory 445, the fault detection result with respect to other than thenon-volatile memory 445 (such as UVLO, OVP, SCP, and OTP), theenabled/disabled state of the gate driver 441, and the output states atthe FLT1 and FLT2 terminals respectively.

Error detection with respect to the non-volatile memory 445 is carriedout chiefly by the error detection-correction circuit ECC. On the otherhand, fault detection with respect to other than the non-volatile memory445 (such as UVLO, OVP, SCP, and OTP), enabled/disabled state switchingfor the gate driver 441, and fault output via the FLT1 and FLT2terminals are carried out chiefly by the fault detector-controller 442.

As shown at line 1, if the adjustment data D1 and D2 written to thenon-volatile memory 445 is normal and in addition no fault is detectedwith respect to other than the non-volatile memory 445, the gate driver441 performs normal operation. In this case, the FLT1 and FLT2 terminalsare both in a high-impedance state, and thus the external fault signalsFLT1 and FLT2 delivered to the ECU 2 are, by being pulled-up by theresistors R1 and R2, at high level (the logic level indicating normalcondition).

As shown at line 2, if the adjustment data D1 and D2 written to thenon-volatile memory 445 is normal but a fault is detected with respectto other than the non-volatile memory 445, then, regardless of the errordetection result, the FLT1 terminal is kept at low level (the outputstate indicating a fault being detected) and the gate driver 441 isforcibly stopped. It is thus possible, while ensuring the safety of theelectric vehicle, to promptly notify the ECU 2 of the occurrence of someserious fault (such as UVLO, OVP, SCP, or OTP) in the isolated gatedriver 1 or the high-side switch SWH. Since the adjustment data D1 andD2 has no error, the FLT2 terminal remains in a high-impedance state.

As shown at line 3, if a one-bit error is detected in the adjustmentdata D1 and D2 written to the non-volatile memory 445 and in addition nofault is detected elsewhere than in the non-volatile memory 445, theFLT2 terminal is kept at low level (the logic level indicating an errorbeing detected) and the gate driver 441 continues normal operation. TheFLT1 terminal remains in a high-impedance state. In this way, a one-biterror can be detected and corrected by the error detection-correctioncircuit ECC, and thus the normal operation of the gate driver 441, andhence the traveling of the electric vehicle, can be continued with noproblem. Moreover, with the FLT2 terminal dropped to low level, it ispossible to notify the electric vehicle's driver of a sign of abreakdown.

As shown at line 4, if a one-bit error is detected in the adjustmentdata D1 and D2 written to the non-volatile memory 445 and in additionalso a fault is detected elsewhere than in the non-volatile memory 445,the FLT1 and FLT2 terminals are both kept at low level and the gatedriver 441 is forcibly stopped. In this way, if a fault is detectedelsewhere than in the non-volatile memory 445, as in the case shown atline 1 and described previously, regardless of the error detectionresult, the FLT1 terminal is kept at low level (the output stateindicating a fault being detected), the gate driver 441 is forciblystopped. It is thus possible, while ensuring the safety of the electricvehicle, to promptly notify the ECU 2 of the occurrence of some seriousfault (such as UVLO, OVP, SCP, or OTP) in the isolated gate driver 1 orthe high-side switches SWH.

As shown at line 5, if a two-or-more-bit error is detected in theadjustment data D1 and D2 written to the non-volatile memory 445, then,regardless of the fault detection result with respect to other than thenon-volatile memory 445, the FLT1 and FLT2 terminals are both kept atlow level and the gate driver 441 is forcibly stopped. In this way, if atwo-or-more-bit error occurs, it is impossible to correct the adjustmentdata D1 and D2 and thus to perform characteristics adjustment for theisolated gate driver 1 properly. It is therefore of the highest priorityto forcibly stop the gate driver 441 to ensure the safety of theelectric vehicle.

Moreover, by dropping the external fault signal FLT1 to low level, it ispossible to promptly indicate the ECU 2 of the occurrence of someserious fault in the isolated gate driver 1 or the high-side switch SWH(here, a two-or-more-bit error in the non-volatile memory 445 and theresulting forcible stop of the gate driver 441). In these respects, thisoperation example is no different from the first and second operationexamples (FIGS. 16 and 17 respectively) described previously.

FIG. 19 is a table showing a fourth operation example of fault outputand, like FIG. 18 referred to previously, shows the error detectionresult with respect to the non-volatile memory 445, the fault detectionresult with respect to other than the non-volatile memory 445 (such asUVLO, OVP, SCP, and OTP), the enabled/disabled state of the gate driver441, and the output states at the FLT1 and FLT2 terminals respectively.

The fourth operation example shown in the diagram is basically similarto the third operation example (FIG. 18 ) described previously, the onlydifference being that, if a two-or-more-bit error is detected in theadjustment data D1 and D2 written to the non-volatile memory 445, theFLT2 terminal is kept in a high-impedance state. In this way, ondetection of a two-or-more-bit error, the FLT1 terminal is used toperform fault output for the ECU 2; thus, the output state at the FLT2terminal does not matter.

<Sharing of a Fault Signal Output Terminal>

In the first to fourth operation examples (FIGS. 16 to 19 ) describedpreviously, if with respect to the adjustment data D1 and D2 written tothe non-volatile memory 445 a one-bit error is detected, the FLT2terminal is used to perform fault output (sign-of-breakdownnotification) and, if a two-or-more-bit error is detected, the FLT1terminal is used to perform fault output (breakdown notification). Here,these two kinds of fault output can be performed via the FLT2 terminalalone, while the FLT1 terminal is left uninvolved. Now, with referenceto the relevant diagrams, a description will be given of examples inwhich the FLT2 terminal is shared.

FIG. 20 is a diagram showing a first example of sharing a fault signaloutput terminal (here, the FLT2 terminal). As shown there, the faultdetector-controller 442 can, if the adjustment data D1 and D2 is normal,keep the FLT2 terminal at high level (e.g., VCC1); if a one-bit error isdetected in the adjustment data D1 and D2, keep the FLT2 terminal atmiddle level (e.g., VCC1/2); and if a two-or-more-bit error is detectedin the adjustment data D1 and D2, keep the FLT2 terminal at low level(e.g., GND1). With this configuration, it is possible to recognize theresult of error detection based on the voltage level at the FLT2terminal.

FIG. 21 is a diagram showing a second example of sharing a fault signaloutput terminal (here, the FLT2 terminal). As shown there, the faultdetector-controller 442 can, if the adjustment data D1 and D2 is normal,hold the FLT2 terminal at high level; if a one-bit error is detected inthe adjustment data D1 and D2, pulse-drive (oscillate) the FLT2 terminalbetween high and low levels; and if a two-or-more-bit error is detectedin the adjustment data D1 and D2, hold the FLT2 terminal at low level.With this configuration, it is possible to recognize the result of errordetection based on the logic level at the FLT2 terminal and whether itis oscillated.

FIG. 22 is a diagram showing a third example of sharing a fault signaloutput terminal (here, the FLT2 terminal). As shown there, the faultdetector-controller 442 can, if the adjustment data D1 and D2 is normal,hold the FLT2 terminal at high level; if a one-bit error is detected inthe adjustment data D1 and D2, pulse-drive (oscillate) the FLT2 terminalat a pulse frequency f1; and if a two-or-more-bit error is detected inthe adjustment data D1 and D2, pulse-drive the FLT2 terminal at a pulsefrequency f2 (e.g., f2>f1). With this configuration, it is possible torecognize the result of error detection based on the logic level and thepulse frequency at the FLT2 terminal.

While no more illustration will be given, a fault signal output terminalcan be shared in any manner other than as described above, by changingthe output state at the FLT2 terminal as desired according to the resultof error detection with respect to the adjustment data D1 and D2. Forexample, a parameter (such as pulse width, duty, or type of modulation)with which the FLT2 terminal is pulse-driven can be changed.

<Application to Electric Vehicles>

FIG. 23 is a diagram showing the exterior appearance of an electricvehicle. As has been described above, the isolated gate driver 1described previously and the traction inverter 400 employing it can beused suitably as a means for driving a motor on an electric vehicle X10.

<Overview>

To follow is an overview of the various embodiments described above.

For example, according to what is disclosed herein, an isolated gatedriver includes: a switch connection terminal configured to have aswitching element externally connected to it; a non-volatile memoryhaving adjustment data written to it; a register configured to store theadjustment data read from the non-volatile memory; a gate drivingcircuit configured to drive the gate of the switching element with acharacteristic set based on a value stored in the register; and acontrol logic circuit configured to keep the gate driving circuit in adisabled state until completion of reading the adjustment data from thenon-volatile memory and storing the adjustment data in the register. (Afirst configuration.)

For another example, according to what is disclosed herein, an isolatedgate driver includes: a switch connection terminal configured to have aswitching element externally connected to it; a memory connectionterminal configured to have externally connected to it a non-volatilememory having adjustment data written to it; a register configured tostore the adjustment data read from the non-volatile memory; a gatedriving circuit configured to drive the gate of the switching elementwith a characteristic set based on a value stored in the register; and acontrol logic circuit configured to keep the gate driving circuit in adisabled state until completion of reading the adjustment data from thenon-volatile memory and storing the adjustment data in the register. (Asecond configuration.)

The isolated gate driver of the first or second configuration describedabove may further include: a fault detector configured to detect a faultwith the characteristic set based on the value stored in the register.(A third configuration.)

In the isolated gate driver of any of the first to third configurationsdescribed above, the control logic circuit may be configured to startreading the adjustment data from the non-volatile memory after, as thesupply voltage fed to the isolated gate driver rises, UVLO is canceled;continues storing the adjustment data in the register while keeping thegate driving circuit in the disabled state until completion of storingthe adjustment data in the register; and cancel the disabled state ofthe gate driving circuit on completion of storing the adjustment data inthe register. (A fourth configuration.)

In the isolated gate driver of any of the first, third, and fourthconfigurations described above, the following may be sealed in a singlepackage: a first semiconductor chip having the circuit elements of aprimary circuit system integrated in it; a second semiconductor chiphaving the circuit elements of a secondary circuit system integrated init; and a third semiconductor chip having integrated in it an insulatingelement for transmitting a signal between, while isolating between, thefirst and second semiconductor chips. (A fifth configuration.)

In the isolated gate driver of the second configuration described above,the following may be sealed in a single package: a first semiconductorchip having the circuit elements of a primary circuit system integratedin it; a second semiconductor chip having the circuit elements of asecondary circuit system integrated in it; and a third semiconductorchip having integrated in it an insulating element for transmitting asignal between, while isolating between, the first and secondsemiconductor chips. (A sixth configuration.)

In the isolated gate driver of the fifth or sixth configurationdescribed above, the register and the gate driving circuit may both beintegrated in the second semiconductor chip. (A seventh configuration.)

For another example, according to what is disclosed herein, a tractioninverter includes: the isolated gate driver of the first configurationdescribed above; and the switching element externally connected to theswitch connection terminal of the isolated gate driver, the switchingelement being configured to have its gate driven by the isolated gatedriver. (An eighth configuration.)

For another example, according to what is disclosed herein, a tractioninverter includes: the isolated gate driver of the second configurationdescribed above; the switching element externally connected to theswitch connection terminal of the isolated gate driver, the switchingelement being configured to have its gate driven by the isolated gatedriver; and the non-volatile memory externally connected to the memoryconnection terminal of the isolated gate driver, the non-volatile memorybeing configured to store the adjustment data for the isolated gatedriver. (A ninth configuration.)

For another example, according to what is disclosed herein, a tractioninverter includes: a plurality of the isolated gate drivers of the sixthconfiguration described above; a plurality of the switching elementsexternally connected to a plurality of the switch connection terminalsprovided at the second-semiconductor-chip side of the plurality of theisolated gate drivers respectively, the plurality of the switchingelements being configured to have their gates driven by the plurality ofthe isolated gate drivers respectively; and a plurality of thenon-volatile memories externally connected to a plurality of the memoryconnection terminals provided at the second-semiconductor-chip side ofthe plurality of the isolated gate drivers respectively, the pluralityof the non-volatile memories being configured to store the adjustmentdata for the plurality of the isolated gate drivers respectively. (Atenth configuration.)

For another example, according to what is disclosed herein, a tractioninverter includes: a plurality of the isolated gate drivers of the sixthconfiguration described above; a plurality of the switching elementsexternally connected to a plurality of the switch connection terminalsprovided at the second-semiconductor-chip side of the plurality of theisolated gate drivers respectively, the plurality of the switchingelements being configured to have their gates driven by the plurality ofthe isolated gate drivers respectively; and a single non-volatile memoryas the non-volatile memory externally connected to all of a plurality ofthe memory connection terminals provided at the first-semiconductor-chipside of the plurality of the isolated gate drivers, the non-volatilememory being configured to store the adjustment data for all of theplurality of the isolated gate drivers. (An eleventh configuration.)

For another example, according to what is disclosed herein, an electricvehicle includes: the traction inverter of any of the eighth to eleventhconfigurations described above. (A twelfth configuration.)

For another example, according to what is disclosed herein, an isolatedgate driver includes: a switch connection terminal configured to have aswitching element externally connected to it; a non-volatile memoryhaving adjustment data written to it; a register configured to store theadjustment data read from the non-volatile memory; a gate drivingcircuit configured to drive the gate of the switching element with acharacteristic set based on a value stored in the register; a faultdetector configured to perform fault detection with respect to otherthan the non-volatile memory; an error detection-correction circuitconfigured to perform error detection and error correction with respectto the adjustment data written to the non-volatile memory; a firstexternal terminal configured to externally output the result of thefault detection; a second external terminal configured to externallyoutput the result of the error detection; and a fault controllerconfigured to, if a one-bit error is detected in the adjustment data,bring the second external terminal into an error-indicating output stateand continue with normal operation of the gate driving circuit and, if atwo-or-more-bit error is detected, forcibly stop the gate drivingcircuit. (A thirteenth configuration.)

For another example, according to what is disclosed herein, an isolatedgate driver includes: a switch connection terminal configured to have aswitching element externally connected to it; a memory connectionterminal configured to have externally connected to it a non-volatilememory having adjustment data written to it; a register configured tostore the adjustment data read from the non-volatile memory; a gatedriving circuit configured to drive the gate of the switching elementwith a characteristic set based on a value stored in the register; afault detector configured to perform fault detection with respect toother than the non-volatile memory; an error detection-correctioncircuit configured to perform error detection and error correction withrespect to the adjustment data written to the non-volatile memory; afirst external terminal configured to externally output the result ofthe fault detection; a second external terminal configured to externallyoutput the result of the error detection; and a fault controllerconfigured to, if a one-bit error is detected in the adjustment data,bring the second external terminal into an error-indicating output stateand continue with normal operation of the gate driving circuit and, if atwo-or-more-bit error is detected, forcibly stop the gate drivingcircuit. (A fourteenth configuration.)

In the isolated gate driver of the thirteenth or fourteenthconfiguration described above, the fault controller may be configuredto, if a two-or-more-bit error is detected in the adjustment data, bringthe first external terminal into a fault-indicating output stateregardless of the result of the fault detection. (A fifteenthconfiguration.)

In the isolated gate driver of any of the thirteenth to fifteenthconfigurations described above, the fault controller may be configuredto, if a fault is detected with respect to other than the non-volatilememory, bring the first external terminal into a fault-indicating outputstate regardless of the result of the error detection and forcibly stopthe gate driving circuit. (A sixteenth configuration.)

Or, in the isolated gate driver of the thirteenth or fourteenthconfiguration described above, the fault controller may be configuredto, if a one-bit error is detected in the adjustment data, bring thesecond external terminal into a first output state and, if atwo-or-more-bit error is detected in the adjustment data, bring thesecond external terminal into a second output state different from thefirst output state. (A seventeenth configuration.)

In the isolated gate driver of any of the thirteenth and fifteenth toseventeenth configurations described above, the following may be sealedin a single package: a first semiconductor chip having circuit elementsof a primary circuit system integrated in it; a second semiconductorchip having circuit elements of a secondary circuit system integrated init; and a third semiconductor chip having integrated in it an insulatingelement for transmitting a signal between, while isolating between, thefirst and second semiconductor chips. (A eighteenth configuration.)

In the isolated gate driver of the fourteenth configuration describedabove, the following may be sealed in a single package: a firstsemiconductor chip having circuit elements of a primary circuit systemintegrated in it; a second semiconductor chip having circuit elements ofa secondary circuit system integrated in it; and a third semiconductorchip having integrated in it an insulating element for transmitting asignal between, while isolating between, the first and secondsemiconductor chips. (A nineteenth configuration.)

In the isolated gate driver of the eighteenth to nineteenthconfiguration described above, the register and the gate driving circuitmay both be integrated in the second semiconductor chip. (A twentiethconfiguration.)

For another example, according to what is disclosed herein, a tractioninverter includes: the isolated gate driver of the thirteenthconfiguration described above; and the switching element externallyconnected to the switch connection terminal of the isolated gate driver,the switching element being configured to have its gate driven by theisolated gate driver. (A twenty-first configuration.)

For another example, according to what is disclosed herein, a tractioninverter includes: the isolated gate driver of the fourteenthconfiguration described above; the switching element externallyconnected to the switch connection terminal of the isolated gate driver,the switching element being configured to have its gate driven by theisolated gate driver; and the non-volatile memory externally connectedto the memory connection terminal of the isolated gate driver, thenon-volatile memory being configured to store the adjustment data forthe isolated gate driver. (A twenty-second configuration.)

For another example, according to what is disclosed herein, a tractioninverter includes: a plurality of the isolated gate drivers of thenineteenth configuration described above; a plurality of the switchingelements externally connected to a plurality of the switch connectionterminals provided at the second-semiconductor-chip side of theplurality of the isolated gate drivers respectively, the plurality ofthe switching elements being configured to have their gates driven bythe plurality of the isolated gate drivers respectively; and a pluralityof the non-volatile memories externally connected to a plurality of thememory connection terminals provided at the second-semiconductor-chipside of the plurality of the isolated gate drivers respectively, theplurality of the non-volatile memories being configured to store theadjustment data for the plurality of the isolated gate driversrespectively. (A twenty-third configuration.)

For another example, according to what is disclosed herein, a tractioninverter includes: a plurality of the isolated gate drivers of thenineteenth configuration described above; a plurality of the switchingelements externally connected to a plurality of the switch connectionterminals provided at the second-semiconductor-chip side of theplurality of the isolated gate drivers respectively, the plurality ofthe switching elements being configured to have their gates driven bythe plurality of the isolated gate drivers respectively; and a singlenon-volatile memory as the non-volatile memory externally connected toall of a plurality of the memory connection terminals provided at thefirst-semiconductor-chip side of the plurality of the isolated gatedrivers, the non-volatile memory being configured to store theadjustment data for all of the plurality of the isolated gate drivers.(A twenty-fourth configuration.)

For another example, according to what is disclosed herein, an electricvehicle includes: the traction inverter of any of the twenty-first totwenty-fourth configurations described above. (A twenty-fifthconfiguration.)

According to the invention disclosed herein, it is possible to providean isolated gate driver that contributes to size reduction and costreduction of sets, and to provide traction inverters and electricvehicles that employ such isolated gate drivers.

<Further Modifications>

The embodiments described above deal with examples where an isolatedgate driver is applied to a traction inverter incorporated in anelectric vehicle. This however is not meant to limit the application ofisolated gate drivers, which find wide applications in industrialequipment, medical equipment, and the like.

What is disclosed herein as to the implementation of a non-volatilememory and as to novel start-up sequences and fault output in thatconnection can be applied not only to isolated gate drivers but tosignal transmission devices in general, regardless of whether they areof an insulated or non-insulated type.

The various technical features disclosed herein may be implemented inany manners other than as in the embodiments described above, and allowfor many modifications without departure from the spirit of theirtechnical ingenuity. That is, the embodiments described above should beunderstood to be in every aspect illustrative and not restrictive, andthe technical scope of the present invention is defined not by thedescription of the embodiments given above but by the appended claimsand encompasses any modifications within a scope equivalent insignificance to what is claimed.

1. An isolated gate driver, comprising: a switch connection terminalconfigured to have a switching element externally connected thereto; anon-volatile memory having adjustment data written thereto; a registerconfigured to store the adjustment data read from the non-volatilememory; a gate driving circuit configured to drive a gate of theswitching element with a characteristic set based on a value stored inthe register; a fault detector configured to perform fault detectionwith respect to other than the non-volatile memory; an errordetection-correction circuit configured to perform error detection anderror correction with respect to the adjustment data written to thenon-volatile memory; a first external terminal configured to externallyoutput a result of the fault detection; a second external terminalconfigured to externally output a result of the error detection; and afault controller configured to, if a one-bit error is detected in theadjustment data, bring the second external terminal into anerror-indicating output state and continue with normal operation of thegate driving circuit and, if a two-or-more-bit error is detected in theadjustment data, forcibly stop the gate driving circuit.
 2. An isolatedgate driver, comprising: a switch connection terminal configured to havea switching element externally connected thereto; a memory connectionterminal configured to have externally connected thereto a non-volatilememory having adjustment data written thereto; a register configured tostore the adjustment data read from the non-volatile memory; a gatedriving circuit configured to drive a gate of the switching element witha characteristic set based on a value stored in the register; a faultdetector configured to perform fault detection with respect to otherthan the non-volatile memory; an error detection-correction circuitconfigured to perform error detection and error correction with respectto the adjustment data written to the non-volatile memory; a firstexternal terminal configured to externally output a result of the faultdetection; a second external terminal configured to externally output aresult of the error detection; and a fault controller configured to, ifa one-bit error is detected in the adjustment data, bring the secondexternal terminal into an error-indicating output state and continuewith normal operation of the gate driving circuit and, if atwo-or-more-bit error is detected in the adjustment data, forcibly stopthe gate driving circuit.
 3. The isolated gate driver according to claim1, wherein the fault controller is configured to, if a two-or-more-biterror is detected in the adjustment data, bring the first externalterminal into a fault-indicating output state regardless of the resultof the fault detection.
 4. The isolated gate driver according to claim1, wherein the fault controller is configured to, if a fault is detectedwith respect to other than the non-volatile memory, bring the firstexternal terminal into a fault-indicating output state regardless of theresult of the error detection and forcibly stop the gate drivingcircuit.
 5. The isolated gate driver according to claim 1, wherein thefault controller is configured to, if a one-bit error is detected in theadjustment data, bring the second external terminal into a first outputstate and, if a two-or-more-bit error is detected in the adjustmentdata, bring the second external terminal into a second output statedifferent from the first output state.
 6. The isolated gate driveraccording to claim 1, wherein a first semiconductor chip having circuitelements of a primary circuit system integrated therein, a secondsemiconductor chip having circuit elements of a secondary circuit systemintegrated therein, and a third semiconductor chip having integratedtherein an insulating element for transmitting a signal between, whileisolating between, the first and second semiconductor chips are sealedin a single package.
 7. The isolated gate driver according to claim 2,wherein a first semiconductor chip having circuit elements of a primarycircuit system integrated therein, a second semiconductor chip havingcircuit elements of a secondary circuit system integrated therein, and athird semiconductor chip having integrated therein an insulating elementfor transmitting a signal between, while isolating between, the firstand second semiconductor chips are sealed in a single package.
 8. Theisolated gate driver according to claim 6, wherein the register and thegate driving circuit are both integrated in the second semiconductorchip.
 9. A traction inverter, comprising: the isolated gate driveraccording to claim 1; and the switching element externally connected tothe switch connection terminal of the isolated gate driver, theswitching element being configured to have a gate thereof driven by theisolated gate driver.
 10. A traction inverter, comprising: the isolatedgate driver according to claim 2; the switching element externallyconnected to the switch connection terminal of the isolated gate driver,the switching element being configured to have a gate thereof driven bythe isolated gate driver; and the non-volatile memory externallyconnected to the memory connection terminal of the isolated gate driver,the non-volatile memory being configured to store the adjustment datafor the isolated gate driver.
 11. A traction inverter, comprising: aplurality of the isolated gate drivers according to claim 7; a pluralityof the switching elements externally connected to a plurality of theswitch connection terminals provided at a second-semiconductor-chip sideof the plurality of the isolated gate drivers respectively, theplurality of the switching elements being configured to have gatesthereof driven by the plurality of the isolated gate driversrespectively; and a plurality of the non-volatile memories externallyconnected to a plurality of the memory connection terminals provided atthe second-semiconductor-chip side of the plurality of the isolated gatedrivers respectively, the plurality of the non-volatile memories beingconfigured to store the adjustment data for the plurality of theisolated gate drivers respectively.
 12. A traction inverter, comprising:a plurality of the isolated gate drivers according to claim 7; aplurality of the switching elements externally connected to a pluralityof the switch connection terminals provided at asecond-semiconductor-chip side of the plurality of the isolated gatedrivers respectively, the plurality of the switching elements beingconfigured to have gates thereof driven by the plurality of the isolatedgate drivers respectively; and a single non-volatile memory as thenon-volatile memory externally connected to all of a plurality of thememory connection terminals provided at a first-semiconductor-chip sideof the plurality of the isolated gate drivers, the non-volatile memorybeing configured to store the adjustment data for all of the pluralityof the isolated gate drivers.
 13. An electric vehicle, comprising: thetraction inverter according to claim 9.